NVIDIA Corp. announced today that it has recognized the University of Maryland as a CUDA Center of Excellence, placing it in an elite grouping of 9 other universities and research organizations worldwide. The university was selected for its pioneering use of GPU computing and the CUDA programming model across research and teaching efforts within multiple science and engineering departments.

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A project that aims to revolutionise the design of technologies for supporting research has been awarded a grant of 1.7 million (about $2.6 million) by the UK’s Engineering and Physical Sciences Research Council and the Arts and Humanities Research Council through the RCUK Digital Economy programme.
The multidisciplinary project, entitled PATINA (Personal Architectonics of Interfaces to Artefacts) will be led by the University of Bristol in collaboration with the Universities of Brighton, Greenwich, Newcastle, Southampton and Swansea.

The project includes involvement from Microsoft Research, Nokia Research and the Victoria and Albert Museum.

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Power efficiency is the single biggest challenge facing the mobile handset industry, and collaboration is needed to enable the industry to deliver a required 100X improvement in power efficiency for mobile devices, according to a keynote presentation at the International Solid State Circuits Conference (ISSCC) here Monday (Feb. 8).

Greg Delagi, senior vice president of wireless at Texas Instruments Inc., said the future vision of always on, always connected mobile computing depends heavily on engineers’ ability to improve power efficiency through techniques such as ultra-low voltage and power circuits, high-efficiency DC-DC and DAC converters, SRAM, non-volatile memory and parallel architectures. He outlined promising research in areas such as ultra-low power video codecs, DC-DC converters, medical processors and energy scavenging—the ability to generate power from the surrounding environment—which he called the “holy grail.”

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By Agam Shah
Advanced Micro Devices will put more focus on tightly integrating graphics processor cores into mainstream servers starting 2012 as it tries to increase system performance, a company executive said.

Mainstream servers in the future could have a combination of graphics processors and CPUs in servers as applications take advantage of thousands of GPU cores, said Gina Longoria, director of the product management and workstation division at AMD. The company may provide CPUs and GPUs together in a server to run highly parallel applications, she said.

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Embedded designers will only be able to exploit the potential of multicore processor architectures if the applications software takes advantage of parallelism. This was the starting point for the Massively Parallel Computing seminar held during IP/ESC09 in December 2009.

Massively parallel computing architectures and parallel programming are not new, even in the embedded world – remember the Transputer? So why are they an issue now?

Session chair Huy Nam Nguyen commented: “The performance potential of single chip multicore devices, combined with their low power and small size, has created an expectation. In the embedded world, until now, engineers could cope with developing limited multiprocessor systems using manual design and implementation techniques.” But now, Nguyen inferred, architectural and methodology changes are needed.

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By Sharon Gaudin
After about a year of delays, Intel Corp. today took the wrappers off its high-end Itanium processor, which is code-named Tukwila.

The new Itanium 9300 processor originally was slated to be released early in 2009, but that timetable slipped twice last year. The timing turned out to benefit Intel a bit, because Tukwila ended up arriving on the same day as IBM’s long-anticipated new Power7 processor.

“It’s good that Intel finally stepped up and delivered Tukwila and that the chip is shipping with the promised tweaks that caused the delays,” said Dan Olds, an analyst at Gabriel Consulting Group Inc. “However, competitors haven’t been standing still. IBM had two revs of its Power processor during this time, with the second rev coming out today. So Intel is still playing catch-up in this market.”

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By Mark Fontecchio
IBM rolled out four servers based on its new multicore Power7 processor at an event in New York on Monday, claiming superiority in the shrinking — but still substantial — Unix market.
The news comes a week after Oracle Corp. outlined plans to push the Sun Microsystems Sparc-Solaris combo as the foundation for high-end, data center appliances.

Despite confusion about Oracle’s acquisition of Sun Microsystems, Solaris remains the top Unix OS in server shipments. It runs on both x86 and Sparc servers, while IBM AIX and HP-UX run on only Power and Itanium/PA-RISC chips, respectively. In terms of revenue, however, AIX, however, leads the Unix market

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By Richard Adhikari
IBM’s new Power7 processors provide the foundation for several new Unix server offerings from the company. Each Power7 processor has up to eight cores and four threads per core. Power7 also features “TurboCore” mode and has “intelligent threads,” meaning the number of threads varies depending on the workload.

IBM on Monday launched a one-two punch with its new Power7 processors, which the company claims have twice the performance of the Power6 line but consume less power. A Power7 ceramic module with a lid is shown here bottom side facing up. Each Power7 processor contains eight cores, with four threads per core. These processors power IBM’s Unix servers, four new models of which were also unveiled Monday in a move that might strengthen IBM’s position in the Unix server market.

The Power7’s Tech Specs
The Power7 uses a 45 nanometer process. Each Power7 processor has up to eight cores and four threads per core. That’s four times the maximum number of cores and eight times the number of threads per chip as the Power6.

The Power7 has a TurboCore mode, which is optimized for database and other transaction-oriented workloads. This runs with four cores active and with most of the resources from the other four cores behind the eight active cores. Doing this gives the four active cores more cache memory and memory bandwidth and increases their clock speeds.

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Intel Corp. has a significant, if temporary, edge over archrival Advanced Micro Devices based on news and papers emerging here Monday (Feb. at the International Solid State Circuits Conference (ISSCC).

Intel described at ISSCC its first 32nm server processor to use six cores. Meanwhile AMD discussed a new core it will use in its first processor to combine x86 and graphics cores called Llano. Separately, Intel announced Monday its long-delayed Itanium 9300. It is Intel’s first Itanium chip to use the company’s QuickPath Interconnect letting OEMs link eight multicore processors with additional logic. To date, AMD has been limited to linking four chips in a symmetric multiprocessing system without the need for extra chips.

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Consumers will be able to fix their automobiles while the car gives step-by-step advice, attack their ailments by making computer models of various treatments to find the best one and duck into virtual fitting rooms to try on a store’s clothes without leaving home.

All that and much more will be possible - in some cases within a few years - because of a major shift in computer-chip design, according to Intelscientists and others. And as the technology evolves, these experts believe, the relationship people have with their computers and other devices will undergo a remarkable transformation.

“The machines we build will be capable of understanding the world around us much as we do as humans,” said Justin Rattner, chief technology officer at Santa Clara, Calif.-based chipmaker Intel Corp. “They will see and they will hear and they will probably speak and do a number of other things that resemble humanlike capabilities.”

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by Grant Martin
The Design Automation and Test in Europe 2010 conference will be held in Dresden Germany from March 8 to 12. DATE has many interesting things to offer attendees. Here are some technical sessions that look interesting:

6.8 PANEL SESSION – The Challenges of Heterogeneous Multi-Core Debug
7.8 PANEL SESSION - Who is closing the Embedded Software Design Gap?
Keynotes by Alberto Sangiovanni-Vincentelli and Herman Eul
Session 3.4, “Application Development for Multicores”
Session 8.3, “System Modelling for Design Space Exploration and Validation”
Session 9.3, “Language Based Approaches to System Level Design”
Session 10.4, “Architectures for Next Generation Wireless Communication”

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More Research Papers

By Cristian F. Dumitrescu
Minimizing/hiding the latency of complex or I/O intensive operations
Apart from common operations performed by any network processing intensive application (see Part 1), packet processing involves some specific operations that cannot be efficiently implemented with a general purpose instruction set.
…
When using the pipeline model, each stage of the pipeline must still meet the packet budget, but the amount of processing that needs to fit into this number of clock cycles is limited to the one of the current pipeline stage as opposed to the full packet processing implemented by the entire system.

As a result of each pipeline stage processing a different packet, the packet budget is effectively multiplied with the number of pipeline stages.

When using the cluster model, the cluster is still required to process one packet per each packet budget interval, but by using internally several cores running in parallel, each one processing a different packet, the packet budget is effectively multiplied with the number of cores within the cluster.

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By Cristian F. Dumitrescu
With the advent of the latest generation of multi-core processors it has become feasible from the performance as well as from the power consumption point of view to build complete packet processing applications using general purpose architecture processors, rather than dedicated ASIC and ASSP SoCs.

Architects and developers in the industry are now considering these processors as an attractive choice for implementing a wide range of networking applications, as performance levels that could previously be obtained only with network processors (NPUs) or ASICs can now also be achieved with multi-core architecture processors, but without incurring the disadvantages of the former.

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A 100-GHz transistor has been demonstrated by IBM Research. Fabricated on new 2-inch graphene wafers and operating at room temperature, the RF graphene transistors are said to beat the speeds of all but the fastest GaAs transistors, paving the way to commercialization of high-speed, carbon-based electronics.

“There are all kinds of extraordinary claims being made every day for graphene semiconductors, but this is the first demonstration of a radio frequency graphene transistor that was made under technologically relevant conditions and scale,” said IBM Fellow Phaedon Avouris, who oversees carbon-based materials efforts at IBM Research (Yorktown Heights, N.Y.).

The graphene RF transistors were created for the Defense Advanced Research Project Agency under its Carbon Electronics for RF Applications (CERA) program. Almost four times faster than previous demonstrations, the graphene transistors were fabricated at the wafer scale using epitaxially grown graphene processing techniques that are compatible with those used to fabricate silicon transistors.

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By Larry Greenemeier
Microsoft and the National Science Foundation (NSF) on Thursday announced plans to offer researchers and research groups selected through the agency’s merit review process free access to computer servers. Microsoft will host the computing infrastructure at its data centers, giving the researchers access to storage, computational and networking resources via the Internet for a period of three years.

Microsoft and the NSF are touting their relationship as a way to provide scientists with a place to write and run software as well as store and search data without having to factor in the cost of these services. Microsoft is offering these computing resources through its Windows Azure platform, which is essentially the company’s way of opening up some of its own data center capacity to outside organizations.

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by John Morris
The six-core version of Westmere will be available in both desktop (Gulftown) and dual-socket server versions. Not surprisingly, it shares a lot of the same features with the dual-core Core i3 and Core i5 Westmeres including Hyper-Threading (12 threads for a six-core chip), Turbo Boost for improved performance on tasks that are not multi-threaded, an integrated memory controller, and features designed to make it more power-efficient.

But there are some differences too. Gulftown does not have a graphics controller in the same package, which makes since given that it is designed for enthusiast desktops and will be paired with discrete graphics. It also has a larger data cache–a total of 12MB of L3 compared with 4MB on the dual-core versions–which when combined with the extra cores results in a chip that is larger and contains 1.17 billion transistors. Intel said it uses some of those extra transistors to speed up tasks such as data encryption and decryption.

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By Michael Parker, Altera Corp.
FPGAs have long been used as primary and co-processors in telecommunications. Digital signal processing (DSP) in industrial applications often has fundamental differences from the typical telecommunication application. In telecommunications, the input data is commonly high data rates with real time processing constraints requiring completion of calculations between successive input data buffers or samples. With a DSP processor, this may allow for only a few tens of instructions per input data sample. This instruction bandwidth limitation can be minimized by taking advantage of the multiple processing units in some DSP processors. However, creating the specialized pipe-lined code to take true advantage of this parallelism requires hand optimization of assembly language routines. Maintenance, re-usability, and implementation of this type of code can be troublesome and expensive at best. Additionally, the degree of parallelism (simultaneous executions) is relatively low, and may still not permit the real time processing constraints to be met.

A better alternative for high-bandwidth computations is to use an FPGA as a co-processor that integrates the repetitive, speed-critical portions of an algorithm into the FPGA. With an FPGA and automated design software, design engineers have the ability to optimize system performance in ways not possible with a traditional DSP. This article discusses the general issues of moving part, or all, of a DSP industrial application onto an FPGA using system software design tools.

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by Mark Hachman
While ARM has so failed to succeed in the netbook market, it is prepping faster, multicore versions of its Cortex processor, running up to speeds of 2 GHz. The goal? Take on Intel’s Atom and cement ARM’s space in the smartphone market.

This week, ARM reported fourth-quarter profits before taxes of about $32 million, down slightly from 2008, while revenues were $489.5 million, down 10 percent on 2008.

However, in its fourth-quarter earnings call, ARM did not mention the Apple iPad, or even Apple, at all. Many had suspected that Apple had licensed an ARM design to use as the centerpiece of its own A4 chip, the heart of the iPad.

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Intel’s disclosure of more details of its upcoming 6-core Gulftown processor earlier today is just one of several moves aimed at adding more cores to the processors used in desktops and servers that we should be seeing over the next few months.

On the desktop front,Intel has said it will ship the desktop version of its 32-nm Gulftown chip, widely expected to be the high end of the Core i7 line, in the first half of the year, with many people expecting the chip in the next couple of months.

But AMD is right behind, with its own 45-nm 6-core chip, known as Thuban, which is slated to be part of its “Leo” platform, also expected in the first half of the year. AMD hasn’t discussed naming either, but it seems likely this would be a Phenom X6.

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Intel will discuss the company’s current “Westmere” 32-nm technology at the International Solid -State Circuit conference next week. But Intel’s own research has been focused on improving the performance of future multi-core chips, including reconfigurable logic.

Intel launched the Westmere technology at the recent Consumer Electronics Show in January. The 32-nm technology, a process shrink from the 45-nm technology originally used in Intel’s “Nehalem” or Core processor line, now is known as the Core i3, Core i5, and Core i7.

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