By Timothy Prickett Morgan, The Register
When Nvidia did a preview of its next-generation “Kepler” GPU chips back in March, the company’s top brass said that they were saving some of the goodies in the Kepler design for the big event at Nvidia’s GPU Technical Conference in San Jose, which runs this week. And true to its word, the Kepler GPUs do have some goodies that will make them considerably more useful for graphics and HPC compute workloads.

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by Damon Poeter, PC Magazine
Jen-Hsun Huang thinks GPU computing is just starting to hit its stride. Kicking off the annual GPU Technology Conference in San Jose, Calif. on Tuesday, Nvidia’s president and chief executive promised that the company’s new Kepler architecture and thriving CUDA ecosystem would continue to “democratize high-performance computing as we know it.”

Nvidia’s evolution from a company that largely catered to hardcore games to one that’s got a finger in everything from scientific computing to smartphones may be one of the most under-reported stories in technology. Back in 2008, when the graphics chip maker first introduced its proprietary CUDA programming language, there was a single Top 500 supercomputer that used its graphics processors.

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By Timothy Prickett Morgan, The Register
After a five-year effort,­ Nvidia is adding graphics virtualization to its latest “Kepler” line of GPUs.

The Kepler GPUs, previewed in the GeForce line back in March, are the stars of the GPU Technical Conference that Nvidia is hosting this week in San José, California – but some of the most interesting news about them was kept under wraps until Tuesday’s keynote by Nvidia cofounder and CEO Jen-Hsun Huang.
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by Anton Shilov, XBit Labs
Freescale Semiconductor this week introduced two 64-bit QorIQ P5 family control plane processors. The quad-core QorIQ P5040 and dual-core P5021 products operate at 2.40GHz and feature a mix of accelerators, high-speed interfaces and security features, resulting in advanced embedded solutions ideally suited for power-conscious control plane applications.
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by Anton Shilov, XBit labs
Every fifth smartphone sold last year featured system-on-chip with two general-purpose cores, according to Strategy Analytics market tracking firm. Samsung leads transition pace to multi-core SoCs for smartphones: 60% of its smartphone chips sold last year are dual-core application processors.

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SAN JOSE, Calif.—GPU Technology Conference—May 14, 2012—NVIDIA today introduced NVIDIA® Nsight™, Eclipse Edition, the world’s first integrated development environment (IDE) for developing GPU accelerated applications on Linux- and Mac OS-based systems.

NVIDIA Nsight provides powerful debugging and profiling tools that enable high performance computing (HPC) and graphics developers to fully optimize the performance of CPUs and GPUs.
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Source: HPCWire
nCore Design, a leading provider of embedded HPC solutions and multicore training courses, today announced plans to present its popular multicore programming course, NCT-500, in Houston, Texas June 11-12, 2012.

The course titled “NCT-500 PGI Accelerator with OpenACC Directives” was developed by nCore in collaboration with The Portland Group (PGI). This course covers concepts and approaches related to programming GPU accelerators using OpenACC directives and the PGI Accelerator ™ programming model. Structured as an interactive workshop, students learn from in-depth, hands-on lectures and laboratories, gaining a keen understanding of how to capitalize on low-cost, high performance GPU computing hardware to improve application performance while reducing maintenance and porting requirements.

NCT-500 is ideal for software architects, developers, team leaders and managers seeking to improve their GPU software skills. As mandatory prerequisites, students should have knowledge of computer architecture and intermediate C or Fortran software development experience.

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In March 2010, the Parallel Programming Community on the Intel Software Network published a collection of technical papers to provide software developers with the most current technical information on Application Threading, Synchronization, Memory Management and Programming Tools.

The Intel Guide for Developing Multithreaded Applications (PDF 2.86MB)
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Eiffel Software announces an international series of one-day seminars led by award-winning technology guru Dr. Bertrand Meyer. Concurrent and Parallel Programming is the next big shift in software development since the adoption of Object Technology nearly a quarter of a century ago. Mastering Concurrent and Parallel Programming is a critical skill for any software developer who wants to build the new “killer apps”.
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Nvidia announced that LLVM, one of the industry’s most popular open-source compilers, now supports Nvidia GPUs, dramatically expanding the range of researchers, independent software vendors (ISVs) and programming languages that can take advantage of the benefits of GPU acceleration.
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The OpenACC standards group today announced growing support for OpenACC-supported development tools, and initial results from programmers who have been using the recently-released OpenACC compilers to accelerate research.
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Release of new Prism Platform Support Package helps developers unlock the power of Renesas’ manycore parallel architecture

CriticalBlue, a provider of embedded multicore software analysis, exploration and verification tools with associated services, announced today the availability of more support for different multicore platforms from Renesas Electronics Corporation , a premier supplier of advanced semiconductor solutions, within its Prism product. Software developers using various Renesas’ multicore platforms can now analyze their existing software applications, quickly evaluate performance on the chosen platform, and accelerate the implementation and tuning of their software on the parallel architecture.
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NVIDIA today announced that LLVM, one of the industry’s most popular open source compilers, now supports NVIDIA GPUs, dramatically expanding the range of researchers, independent software vendors (ISVs) and programming languages that can take advantage of the benefits of GPU acceleration.

LLVM is a widely used open source compiler infrastructure, with a modular design that makes it easy to add support for programming languages and processor architectures. The CUDA(R) compiler provides C, C++ and Fortran support for accelerating application using the massively parallel NVIDIA(R) GPUs. NVIDIA has worked with LLVM developers to provide the CUDA compiler source code changes to the LLVM core and parallel thread execution backend. As a result, programmers can develop applications for GPU accelerators using a broader selection of programming languages, making GPU computing more accessible and pervasive than ever before.

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The new quad-core QorIQ P5040 and dual-core P5021 products feature a robust mix of accelerators, high-speed interfaces and security features, resulting in advanced embedded solutions ideally suited for power-conscious control plane applications.

The new products complement Freescale’s previously announced QorIQ P5020 and P5010 devices based on 2 GHz cores, and round out one of the industry’s most comprehensive portfolios of embedded control plane processors.

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Threading Building Blocks (TBB) is a C++ threading library that makes multicore programming more accessible. We considered TBB for web application developers working in script languages.

Many websites require a non-trivial amount of per-request processing in the application layer, to retrieve, consolidate or manipulate data. Achieving better performance at this level improves response times and the overall user experience.

by Wolfgang Gentzsch, Executive HPC Consultant, HPCWire
In a previous article (We Need More than Multicore), Wolfgang discussed the evolution of multicore processors, and the dramatic effect this processor shift can have on compute cluster performance. Clearly, leveraging a lot of cores will require that many concurrent tasks – as opposed to a single massively parallel task – run safely and predictably within a system. These concurrent tasks will range from serial to multi-threaded to parallel tasks, and all will need to share the same system resources in a productive and reliable manner.

The question becomes how to do this in operating systems (OS) environments that were not designed with multicore architectures in mind. For example, Linux, which has become the pervasive operating OS for servers, is based on time slicing, which is somewhat analogous to suboptimal round-robin server farm dispatch. But it has limitations when running many concurrent tasks that access shared processors and memory. As the number of competing tasks increases, the likelihood of interference between tasks rises exponentially.

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Leading researchers, hardware and software engineers, and high performance computing specialists from around the country attended the TACC-Intel Highly Parallel Computing Symposium on April 10 and 11 at the Texas Advanced Computing Center (TACC) in Austin, Texas. The meeting showcased the experiences of researchers who had ported their scientific computing codes to Intel’s Knights Ferry (KNF) software development platform, the prototype hardware and software development package for Intel’s Many Integrated Core (MIC) architecture — as well as researchers working on the single-chip cloud (SCC).

Over 100 participants from all sectors of the science and technology community attended the symposium and more than 30 stayed on to attend a tutorial on “Preparing for Many Core Programming,” taught by Kent Milfeld, research associate at TACC. By and large, participants expressed enthusiasm for the forthcoming chips based on their early experiences. The symposium followed a series of Intel-led discussions and training sessions held around the world over the last six months in anticipation of the release of Knights Corner, the first product to use the Intel MIC architecture.

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by Patrick Thibodeau, ComputerWorld

At the supercomputing conference here, there’s an almost obsessive focus on developing an exascale computing system — one that would be roughly 1,000 times more powerful than any existing system — before the end of the decade.
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by Anne Trafton, MIT News Office
For decades, scientists have dreamed of building computer systems that could replicate the human brain’s talent for learning new tasks.

MIT researchers have now taken a major step toward that goal by designing a computer chip that mimics how the brain’s neurons adapt in response to new information. This phenomenon, known as plasticity, is believed to underlie many brain functions, including learning and memory.
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by Sylvie Barak, EETimes

Disruptive technologies like the GPU are important steps on the path to exascale computing said Nvidia Corp.’s CEO Jen Hsun Huang in a keynote at SC11 on Tuesday (Nov. 15).

With supercomputing already an essential tool in modern science, Huang said the industry’s work in the space was “vitally important to society and the advancement of culture,” but that reaching exascale was something of an innovator’s dilemma.
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