2009 2008 2007 2006 2005 2004 2003 2002 2001
2000 1999 1998 1997 1996 Prior to 1995 Whitepapers
Papers listed here are either freely available on the web or obtained legally. Please respect the various copyright stipulations placed on these documents. If any author would like us to add or to remove their paper from here, please contact us at info@multicoreinfo.com.
Multicore Papers 2006
Software Development Tools for Multiprocessors [Slides]
Steven A. Guccione
Second Workshop on Architecture Research Using FPGA Platforms (WARFP)
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
Sangyeun Cho and Lei Jin
Proceedings of the IEEE/ACM Int’l Symposium on Microarchitecture (MICRO) 2006
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
James Donald and Margaret Martonosi
Computer Architecture Letters. Volume 5, No. 2. August 2006
Impact of CMP Design on High-Performance Embedded Computing
Patrick Crowley, Mark A. Franklin, Jeremy Buhler and Roger D. Chamberlain
High Performance Embedded Computing Workshop. September 2006
Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors
Matthew DeVuyst, Rakesh Kumar and Dean Tullsen
IPDPS 2006
Power Efficiency for Variation-Tolerant Multicore Processors
James Donald and Margaret Martonosi
International Symposium on Low Power Electronics and Design 2006
Impact of Parameter Variations on Multi-Core Chips
Eric Humenay, David Tarjan and Kevin Skadron
Workshop on Architectural Support for Gigascale Integration 2006
The Software Stack for Transactional Memory: Challenges and Opportunities
Brian Carlstrom, JaeWoong Chung, Christos Kozyrakis, Kunle Olukotun
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
Ubiquitous Stream Programming to Facilitate Migration to Multicore Architectures
Matthew Drake, David Zhang, Michael Gordon, Janis Sermulins, et al.
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
Optimizing Data Parallel Operations on Many-Core Platforms
Byoungro So, Anwar Ghuloum and Youfeng Wu
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
MultiCore Framework: An API for Programming Heterogeneous Multicore Processors
Brian Bouzas, Jon Greene, Robert Cooper, Michael Pepe, et al.
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
Programming Experience on Cyclops-64 Multi-Core Chip Architecture
Ziang Hu, Geoff Gerfin, Brice Dobry, Guang Gao, Univ. of Delaware
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
Understanding Performance of Multi-Core Systems using Trace-based Visualization
Peter F. Sweeney, Matthias Haswirth, Amer Diwan, Marina Biberstein, Yuval Harel
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
Unraveling Data Race Detection in the Intel Thread Checker
Utpal Banerjee, Brian Bliss, Zhiqiang Ma, Paul Petersen, Intel
STMCS: First Workshop on Software Tools for Multi-Core Systems 2006
An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors
Alberto Ros and Manuel E. Acacio and José M. García
ACM International Conference on Computing Frontiers, May 2006
CellSs: A Programming Model for the Cell BE Architecture
Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta
Supercomputing (SC) 2006
Modeling Cache Sharing on Chip Multiprocessor Architectures
Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten
IEEE International Symposium on Workload Characterization, 2006
Issues in Embedded Single-Chip Multicore Architectures
Sandro Bartolini and Roberto Giorgi
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture
David Ródenas, Xavier Martorell, Eduard Ayguadé, et al.
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
John Oliver, Ravishankar Rao, Diana Franklin, et al.
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications
Hamed Fatemi, Bart Mesman, Henk Corporaal, et al.
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor
Pei Gu and Uzi Vishkin.
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Design and architecture for an embedded 32-bit QueueCore
Ben A. Abderazek, Sotaro Kawata and Masahiro Sowa
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Tiny split data-caches make big performance impact for embedded applications
Afrin Naz, Krishna Kavi, Wentong Li and Philip Sweany
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
A dynamically reconfigurable cache for multithreaded processors
Alex Settle, Dan Connors, Enric Gibert and Antonio González
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Exploring power reduction options for a single-chip multiprocessor through system-level modeling
Patrick Anthony La Fratta and James M. Baker, Jr.
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Destructive-read in embedded DRAM, impact on power consumption
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs and Lasse Natvig
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
A low-power cache scheme for embedded computing
Yul Chu, Arul Sandeep Gade and Abhishek Bhaduri
Journal of Embedded Computing, Issues in embedded single-chip multicore architectures, Vol. 2, No. 2. 2006
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
M. K. Qureshi and Yale Patt
MICRO 2006
Evaluating the Performance Impact of Hardware Thread Priorities in Simultaneous Multithreaded Processes using SPEC CPU2000
M. Meswani and P. Teller
Workshop on Operating System Interference In High Performance Applications, 2006
Real-time scheduling on multicore platforms
James H. Anderson, John M. Cal, Umamaheswari C. Devi
IEEE Real-Time and Embedded Technology and Applications Symposium 2006
Why Intel is Designing Multi-Core Processors
Geoff Lowney
Invited Talk at SPAA 2006
Chip-level Integration: The New Frontier for Microprocessor Architecture [Slides from some other talk]
Jaime Moreno
Invited Talk at SPAA 2006
FFT Program Generation for Shared Memory: SMP and Multicore
Franz Franchetti, Yevgen Voronenko, Markus Pueschel
Supercomputing 2006
A Memory Model for Scientific Algorithms on Graphics Processors
Naga Govindaraju, Scott Larsen, Jim Gray, Dinesh Manocha
Supercomputing 2006
Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors
X Shi, Z Yang, Peir JK, L Peng, Chen YK, V Lee, B Liang
IPDPS 2006
SecCMP: A Secure Chip-Multiprocessor Architecture
L. Yang, L. Peng
First Workshop on Architectural and System Support for Improving Software Dependability (ASID)
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture [IEEE login]
Yingping Zhang, Taikyeong Jeong, Fei Chen, Ronny Nitzsche, and Guang R. Gao
IPDPS 2006
Helper Thread Prefetching for Loosely-Coupled Multiprocessor Systems
Changhee Jung Daeseob Lim Jaejin Lee Solihin, Y.
IPDPS 2006
Compatible Phase Co-Scheduling on a CMP of Multi-Threaded Processors
A. El-Moursy, R. Garg, D. H. Albonesi, and S. Dwarkadas
IPDPS 2006
Porting Between Itanium and Sparc Multiprocessing Systems
Lisa Higham and LillAnne Jackson
SPAA 2006
BulletProof: A Defect-Tolerant CMP Switch Architecture
Constantinides, K.Plaza, S. Blome, J.Zhang, B. Bertacco, V. Mahlke, S. Austin, T. Orshansky, M.
HPCA 2006
CMP Design Space Exploration Subject to Physical Constraints
Yingmin Li Lee, B. Brooks, D. Zhigang Hu Skadron, K.
HPCA 2006
Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors
David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, et al.
HPCA 2006
Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors
Jian Li and José F. Martínez
HPCA 2006
Last Level Cache (LLC) Performance of Data Mining Workloads On a CMP — A Case Study of Parallel Bioinformatics Workloads
Aamer Jaleel, Matthew Mattina, Bruce Jacob
HPCA 2006
Construction and Use of Linear Regression Models for Processor Performance Analysis
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil
HPCA 2006
Chip-multiprocessing and Beyond [Slides] [Keynote]
Per Stenström, Chalmers University of Technology
HPCA 2006
The Common Case Transactional Behavior of Multithreaded Programs
JaeWoong Chung, Hassan Chafi, et al.
HPCA 2006
Speculative Synchronization and Thread Management for Fine Granularity
Threads
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover
HPCA 2006
Efficient Instruction Schedulers for SMT Processors
Joseph Sharkey, Dmitry Ponomarev
HPCA 2006
Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? [Keynote]
Yale Patt, University of Texas at Austin
ISCA 2006
Techniques for Multicore Thermal Management: Classification and New Exploration
James Donald, Margaret Martonosi
ISCA 2006
An Integrated Framework for Dependable and Revivable Architecture Using Multicore Processors
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, and Mrinmoy Ghosh
ISCA 2006
Multiple Instruction Stream Processor
Richard A. Hankins, Gautham N. Chinya, et al.
ISCA 2006
Design and Management of 3D Chip Multiprocessors using Network-in-Memory
Feihui Li, C. Nicopoulos, T. Richardson, Yuan Xie, V. Narayanan, M. Kandemir
ISCA 2006
Bulk Disambiguation of Speculative Threads in Multiprocessors
Luis Ceze, James Tuck, Calin Cascaval, Josep Torrellas
ISCA 2006
Learning-Based SMT Processor Resource Distribution via Hill-Climbing
Seungryul Choi, D. Yeung
ISCA 2006
Cooperative Caching for Chip Multiprocessors
Jichuan Chang and Gurindar S. Sohi
ISCA 2006
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors
K. Strauss, Xiaowei Shen, J. Torrellas
ISCA 2006
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Liqun Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian, J.B.
Carter
ISCA 2006
Architectural Support for Operating System-Driven CMP Cache Management
Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
PACT 2006
Communist, Utilitarian, and Capitalist Cache Policies on CMPs:Caches as a Shared Resource
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar Iyer, and Srihari Makineni
PACT 2006
Core architecture Optimization for Heterogeneous Chip Multiprocessors
Rakesh Kumar, Dean M. Tullsen, and Norman P. Jouppi
PACT 2006
Challenges and Opportunities in the Post Single-Thread-Processor Era [Slides]
Steve Scott, Cray
PACT 2006
Efficient Data Protection for Distributed Shared Memory Multiprocessors
Brian Rogers, Milos Prvulovic, and Yan Solihin
PACT 2006
Testing Implementations of Transactional Memory
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi, Austen McDonald, et al.
PACT 2006
Efficient Emulation of Hardware Prefetchers via Event-Driven Helper Threading
Ilya Ganusov and Martin Burtscher
PACT 2006
Adaptive Reorder Buffers for SMT Processors
Joseph Sharkey, Deniz Balkan, and Dmitry Ponomarev
PACT 2006
Efficient Frequent Pattern Mining on Shared Memory Systems: Implications for Chip Multiprocessor Architectures
G. Buehrer, S. Parthasarathy, A. Ghoting, Y.-K. Chen, D. Kim, A. Nguyen,
Memory Systems Performance and Correctness Workshop, Oct. 2006
2009 2008 2007 2006 2005 2004 2003 2002 2001
2000 1999 1998 1997 1996 Prior to 1995 Whitepapers
