2009 2008 2007 2006 2005 2004 2003 2002 2001
2000 1999 1998 1997 1996 Prior to 1995 Whitepapers
Papers listed here are either freely available on the web or obtained legally. Please respect the various copyright stipulations placed on these documents. If any author would like us to add or to remove their paper from here, please contact us at info@multicoreinfo.com.
Multicore Papers 2005
TSIC: Thermal Scheduling Simulator for Chip Multiprocessors
Kyriakos Stavrou and Pedro Trancoso
10th Panhellenic Conference on Informatics (PCI10). Pages 589-599
DDM-CMP: Data Driven Multithreading on a Chip Multiprocessor [Requires Springer login] [Presentation]
Kyriakos Stavrou, Paraskevas Evripidou, and Pedro Trancoso
th International Workshop on Embedded Computer Systems: Architecture, MOdeling and Simulation (SAMOS-V), Samos, Greece, July 2005.
A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors
Huiyang Zhou
Computer Architecture Letters. Volume 4. September 2005
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
B. H. Meyer, J. J. Pieper, JoAnn Paul, J. Nelson, S. Pieper, A. Rowe
IEEE Transactions on Computers. Volume 54, Issue 6. June 2005
An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors
Matthew Curtis-Maury, Xiaoning Ding, Christos Antonopoulos and Dimitrios Nikolopoulos.
IWOMP ‘05. May 2005
Niagara: A 32-way Multithreaded SPARC Processor
Poonacha Kongetira, Kathirgamar Aingaran and Kunle Olukotun
IEEE Micro. March 2005
Scalar Operand Networks
Michael Taylor, Walter Lee, Saman Amarasinghe and Anant Agarwal
IEEE Transactions on Parallel and Distributed Systems. Volume 16, No. 2. February 2005
Effects of Pipeline Complexity on SMT/CMP Power-Performance Efficiency
Ben Lee and David Brooks
WCED-6. June 2005.
Montecito: A Dual-Core, Dual-Thread Itanium Processor
Cameron McNairy and Rohit Bhatia
IEEE Micro. March/April 2005
Heterogeneous Chip Multiprocessors
Rakesh Kumar, Dean Tullsen, Norman Jouppi and Partha Ranganathan
IEEE Computer. November 2005
Scenario-Oriented Design for Single Chip Heterogeneous Multiprocessors
JoAnn Paul
IPDPS ‘05 Workshop 10. April 2005
Future Execution: A Hardware Technique for Prefetching in Chip Multiprocessors
Ilya Ganusov and Martin Burtscher
PACT-2005. September 2005
Maximizing CMP Throughput with Mediocre Cores
John D. Davis, James Laudon and Kunle Olukotun
PACT-2005. September 2005.
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Huiyang Zhou
PACT-2005. September 2005
Optimizing Compiler for a CELL Processor
A. Eichenberger, K. O’Brien, K. K. O’Brien, P. Wu, T. Chen, P. H. Oden, et al.
PACT-2005. September 2005
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
Lawrence Spracklen, Yuan Chou and Santosh Abraham
HPCA-11. February 2005
Distributing the Frontend for Temperature Reduction
Pedro Chaparro, Grigorios Magklis, José González and Antonio González
HPCA-11. February 2005
System Level Methodology for Programming CMP based Multi-threaded Network Processor Architecture
Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler and Karam S. Chatha
VLSI 2005. May 2005
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
Tomer Morad, Uri Weiser, AVnoam Kolodny, Mateo Valero and Eduard Ayguade
Computer Architecture Letters. July 2005
A Case for Increased Operating System Support in Chip Multi-Processors
David Nellans, Rajeev Balasubramonian and Erik Brunvand
P=AC2. September 2005
Code Restructuring for Improving Cache Performance of MPSoCs
Guilin Chen and Mahmut Kandemir
ICCAD ‘05. November 2005.
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
Michael Zhang and Krste Asanovic
ISCA-32. June 2005.
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Zeshan Chishti, Michael Powell and T. N. Vijaykumar
ISCA-32. June 2005
Interconnections in Multi-core Architectures Understanding Mechanisms, Overheads and Scaling
Rakesh Kumar, Victor Zyuban and Dean Tullsen
ISCA-32. June 2005.
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
J Li, J Martinez
ISPASS 2005
Optimizing Inter-processor Data Locality on Embedded Chip Multiprocessors
Guilin Chen and Mahmut Kandemir
EMSOFT ‘05 September 2005
Temperature-sensitive Loop Parallelization for Chip Multiprocessors
Sri Hari Krishna Narayanan, Guilin Chen, Mahmut Kandemir and Yuan Xie
ICCD ‘05. November 2005
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
Yingmin Li, Kevin Skadron, Zhigang Hu and David Brooks
HPCA-11, 2005
Chip Multithreading: Opportunities and Challenges
Lawrence Spracklen and Santosh Abraham
HPCA-11. February 2005
Locality-Conscious Workload Assignment for Array-Based Computations in MPSOC Architectures
Feihui Li and Mahmut Kandemir
DAC-42. June 2005
Mitigating Amdahl’s Law Through EPI Throttling
Murali Annavaram, Ed Grochowski and John Shen
ISCA-32. June 2005.
Fixing the Sequential Bottleneck by Regulating Energy Per Instruction on CMPs
Murali Annavaram, Ed Grochowski and John Shen
Technology@Intel Magazine. October 2005
The Cell Processor Architecture
Peter Hofstee, IBM
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors
Alberto Ros and Manuel E. Acacio and José M. García
11th International Euro-Par Conference, August 2005
Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities
Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC-CMP Processor
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Santosh G. Abraham, and Khoa Nguyen
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
The Cell Processor Architecture
Peter Hofstee, IBM
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
Automatic Thread Extraction with Decoupled Software Pipelining
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
The Future Evolution of High-Performance Microprocessors [Keynote]
Norm Jouppi, HP Labs
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
Store Memory-Level Parallelism Optimizations for Commercial Applications
Yuan Chou, Lawrence Spracklen, Santosh Abraham
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors
Meyrem Krman, Nevin Krman, and José F. Martínez
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
Energy-Efficient Thread-Level Speculation
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck and Josep Torellas
IEEE Micro. January/February 2005
Shader Performance Analysis on a Modern GPU Architecture
Victor Moya del Barrio, Carlos Gonzalez Rodriguez, Jordi Roca Monfort, et al.
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005
CMPs: Now and into the Future [Keynote]
Chuck Moore, (AMD).
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
The RASE (Rapid, Accurate Simulation Environment) for Chip Multiprocessors
John. D. Davis, Cong Fu, James Laudon
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Exploring the Cache Design Space for Large Scale CMPs
Lisa Hsu, Ravi Iyer, Srihari Makineni, Steve Reinhardt, Donald Newell
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Chip Multi-Processor Scalability for Single-Threaded Applications
Vachharajani , Matthew Iyer, Chinmay Ashok, et al.
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Hardware-Modulated Parallelism in Chip Multiprocessors
Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, et al.
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Fast Synchronization For Chip MultiProcessors
Jack Sampson,Ruben Gonzalez, Mike Schlansker, Norm Jouppi, et al.
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Dynamically Configurable Shared CMP Helper Engines for Improved Performance
Anahita Shayesteh, Tim Sherwood, et al.
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Performance Implications of Single Thread Migration on a Chip Multi-Core
Theofanis Constantinou, Yiannakis Sazeides, et al.
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) 2005
Revitalizing Computer Architecture Research
John Shen, Mary Jane Irwin, Todd Austin, et al.
CRA Conference on Grand Research Challenges, 2005
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors [Slides]
Tipp Moseley, Joshua L. Kihm, Daniel A. Connors, and Dirk Grunwald
International Conference on Computer Design, 2005
Performance of multithreaded chip multiprocessors and implications for operating system design
Ra Fedorova, Margo Seltzer, Christopher Small, Daniel Nussbaum
USENIX 2005 Annual Technical Conference
Best of Servers of 2004: Where Multicore Is the Norm
Kevin Krewell
Microprocessor Report. January 2005
Parallel Programming Using Thread-level Speculation
Manohar Prabhu
Doctoral Dissertation, Stanford University, Stanford, CA, December 2005.
Optimizing Compiler for a CELL Processor
Alexandre E. Eichenberger, Kathryn O’Brien, Kevin O’Brien, Peng Wu, et al.
Proc. 14th Int’l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2005, pp. 161-172
Partitioning Multi-Threaded Processors with a Large Number of Threads
A. El-Moursy, R. Garg, D. H. Albonesi, and S. Dwarkadas
International Symposium on Performance Analysis of Systems and Software, March 2005
Intrusion Tolerant and Self-Recoverable Network Service System Using Security Enhanced Chip Multiprocessors
Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Mrinmoy Ghosh, Laura Falk, and Trevor N. Mudge
International Conference on Autonomic Computing, pp.263-273, Seattle, Washington, June, 2005
Muscular Methods for Mammoth Designs
Linda Prowse-Fosler
Vastsystems
Predicting Inter-Thread Cache Contention on a Multi-Processor Architecture
D. Chandra, F. Guo, S. Kim, and Yan Solihin
HPCA 2005
An Approach to Performance Prediction for Parallel Applications
E. İpek, B.R. de Supinski, M. Schulz, S.A. McKee
EURO-PAR 2005
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2000 1999 1998 1997 1996 Prior to 1995 Whitepapers
