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2000 1999 1998 1997 1996 Prior to 1995 Whitepapers
Papers listed here are either freely available on the web or obtained legally. Please respect the various copyright stipulations placed on these documents. If any author would like us to add or to remove their paper from here, please contact us at info@multicoreinfo.com.
Multicore Papers 2004
Thermal Management with Asymmetric Dual Core Designs
Soraya Ghiasi and Dirk Grunwald
University of Colorado Technical Report CU-CS-965-03. June 2004
Scaling to the End of Silicon with EDGE Architectures
D. Burger, S. Keckler, K. McKinley, M. Dahlin, L. John, C. Lin, C. Moore, et al.
IEEE Computer. Volume 37, No 7. July 2004.
Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors
JoAnn Paul, Donald Thomas and Alex Bobrek.
CODES 2004. October 2004
ACCMP - Asymmetric Cluster Chip Multi-Processing
Tomer Morad, Uri Weiser and Avnoam Kolody
CCIT Technical Report #488. June 2004.
Conjoined-core Chip Multiprocessing
Rakesh Kumar, Norman Jouppi , and Dean Tullsen
MICRO-37. December 2004.
Temperature-Aware Design Issues for SMT and CMP Architectures
James Donald and Margaret Martonosi
WCED-5. June 2004
Managing Wire Delay in Large CMP Caches
Bradford Beckman and David Wood
MICRO-37. December 2004
A Case for Shared Instruction Cache on Chip Multiprocessors running OLTP
Partha Kundu, Murali Annavaram, Trung Diep and John Shen
MEDEA-Workshop ‘03. June 2004
Design and Implementation of the POWER5 Microprocessor
J. Clabes, J. Friedrich, M. Sweet, J. Dilullo, S. Chu, D. Plass, J. Dawson, P. Muench, et al.
ISSCC 2004. February 2004
Design and Implementation of the POWER5 Microprocessor
J. Clabes, J. Friedrich, M. Sweet, J. Dilullo, S. Chu, D. Plass, J. Dawson, P. Muench, et al.
DAC-41, 2004
IBM POWER5 Chip: A Dual-Core Multithreaded Processor
Ron Kalla, Balaram Sinharoy and Joel Tendler.
IEEE Micro. March/April 2004
Heat-and-Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System
Michael Powell, Mohamed Gomaa and T.N. Vijaykumar
ASPLOS-XI. October 2004
Helper Threads via Virtual Multithreading On An Experimental Itanium 2 Processor-based
Platform
Perry Wang, Jamison Collins, Hong Wang, Dongkeun Kim, Bill Greene, et al.
ASPLOS-XI. October 2004
Thermal Modeling, Characterization and Management of On-Chip Networks
Li Shang, Li-Shiuan Peh, Amit Kumar and Niraj Jha
MICRO-37, 2004
A Multiprogrammed Workload Model for Energy and Performance Esimation of Adaptive Chip-Multiprocessors
Mladen Nikitovic and Mats Brorsson
IPDPS-18. April 2004
Thermal-Effective Clustered Microarchitectures
Pedro Chaparro, Jose Gonzalez and Antonio Gonzalez
TACS-1. June 2004
Transactional Memory Coherence and Consistency
Lance Hammond, Vicky Wong, Mike Chen, Ben Hertzberg, Brian Carlstrom, Manohar Prabhu, et al.
Proceedings of the 31st annual International Symposium on Computer Architecture (ISCA), 2004
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
Yuan Chou, Brian Fahs, and Santosh Abraham, Sun Microsystems
Proceedings of the 31st annual International Symposium on Computer Architecture (ISCA), 2004
SMTp: An Architecture for Next-generation Scalable Multi-threading
M.Chaudhuri and M. Heinrich
Proceedings of the 31st annual International Symposium on Computer Architecture (ISCA), 2004
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
Proceedings of the 31st annual International Symposium on Computer Architecture (ISCA), 2004
Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems
Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, and Chenghuai Lu
Parallel Architecture and Compilation Techniques, (PACT) pp.123-134, September, 2004
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
S. Kim, D. Chandra, and Y. Solihin
PACT 2004
2009 2008 2007 2006 2005 2004 2003 2002 2001
2000 1999 1998 1997 1996 Prior to 1995 Whitepapers
