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	<title>MulticoreInfo.com</title>
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	<link>http://www.multicoreinfo.com</link>
	<description>The Portal for Multicore Resources</description>
	<pubDate>Fri, 12 Mar 2010 12:30:19 +0000</pubDate>
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		<title>OpenCL Is Ready For The Heavy Lifting</title>
		<link>http://www.multicoreinfo.com/2010/03/opencl-3/</link>
		<comments>http://www.multicoreinfo.com/2010/03/opencl-3/#comments</comments>
		<pubDate>Fri, 12 Mar 2010 12:30:19 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8560</guid>
		<description><![CDATA[by Douglas Eadline, Ph.D.
I was particularly impressed at how fast CUDA has gained traction in HPC and other areas. The CUDA wave has definitely hit the beach and I’ll have more on nVidia as the Fermi GPU begins to filter into the HPC trenches. In this column I want to talk about the other GPU [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/opencl-3/feed/</wfw:commentRss>
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		<item>
		<title>First Intel 6-core CPU benchmarks</title>
		<link>http://www.multicoreinfo.com/2010/03/6-core-benchmarks/</link>
		<comments>http://www.multicoreinfo.com/2010/03/6-core-benchmarks/#comments</comments>
		<pubDate>Fri, 12 Mar 2010 12:16:27 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<category><![CDATA[Performance]]></category>

		<category><![CDATA[Processors]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8558</guid>
		<description><![CDATA[by Agam Shah
Intel has demonstrated its first six-core processor for desktops, the Core i7-980X Extreme Edition, which will go into workstations and enthusiast PCs targeted at gamers.
The company said that the new chip will be faster and more power-efficient compared to its past gaming processors. Based on a new architecture, the processor includes more cores [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/6-core-benchmarks/feed/</wfw:commentRss>
		</item>
		<item>
		<title>What About All Those Cores?</title>
		<link>http://www.multicoreinfo.com/2010/03/all-those-cores/</link>
		<comments>http://www.multicoreinfo.com/2010/03/all-those-cores/#comments</comments>
		<pubDate>Fri, 12 Mar 2010 12:13:08 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8555</guid>
		<description><![CDATA[by Ed Sperling
The introduction of multicore processors in a slew of battery-powered devices is an interesting development. The ARM processor now comes in quad-core configurations, and the Intel Atom processor is now shipping in a dual-core configurations.
We can only assume there will be more cores at each new process node, and probably more cores added [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/all-those-cores/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Virtualization In Your Hand</title>
		<link>http://www.multicoreinfo.com/2010/03/virtualization-2/</link>
		<comments>http://www.multicoreinfo.com/2010/03/virtualization-2/#comments</comments>
		<pubDate>Fri, 12 Mar 2010 12:12:31 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8553</guid>
		<description><![CDATA[By Ed Sperling
The addition of multiple cores inside of computers has created an enormous opportunity for virtualization. Instead of running one operating system or one application, a single server or multicore PC can run multiple virtualized OSes on a single machine at the same time.
From the standpoint of energy efficiency, this has been a huge [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/virtualization-2/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Researchers claim fix for multicore &#8216;concurrency bugs&#8217;</title>
		<link>http://www.multicoreinfo.com/2010/03/concur-bugs/</link>
		<comments>http://www.multicoreinfo.com/2010/03/concur-bugs/#comments</comments>
		<pubDate>Fri, 12 Mar 2010 12:11:41 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[Academia News]]></category>

		<category><![CDATA[Research]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8551</guid>
		<description><![CDATA[American computer researchers say they have developed new software which makes programming of multi-processor machines much easier.
&#8220;With older, single-processor systems, computers behave exactly the same way as long as you give the same commands. Today&#8217;s computers are non-deterministic,&#8221; says Luis Ceze, computer science and engineering prof at the University of Washington, Washington. &#8220;Even if you [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/concur-bugs/feed/</wfw:commentRss>
		</item>
		<item>
		<title>The Long And Painful Path To Power Optimization</title>
		<link>http://www.multicoreinfo.com/2010/03/power-opti-2/</link>
		<comments>http://www.multicoreinfo.com/2010/03/power-opti-2/#comments</comments>
		<pubDate>Fri, 12 Mar 2010 12:08:12 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8549</guid>
		<description><![CDATA[By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.
Perhaps even more [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/power-opti-2/feed/</wfw:commentRss>
		</item>
		<item>
		<title>How to Get a Multicore Processor that&#8217;s Programmer Friendly</title>
		<link>http://www.multicoreinfo.com/2010/03/friendly/</link>
		<comments>http://www.multicoreinfo.com/2010/03/friendly/#comments</comments>
		<pubDate>Wed, 10 Mar 2010 01:14:18 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8547</guid>
		<description><![CDATA[by Steve Leibson
Edward Richards, a Senior Field Applications Engineer for Green Hills Software, had a confession to make at the Real Time Embedded Computing Conference (RTECC) held in Santa Clara recently. No matter the processor architecture in use, he had no more single-core customers in Silicon Valley. All of his clients had moved to multicore [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/friendly/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Does the Cloud Need a Specialized Chip?</title>
		<link>http://www.multicoreinfo.com/2010/03/cloud-chip/</link>
		<comments>http://www.multicoreinfo.com/2010/03/cloud-chip/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 01:10:17 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[Chip Tech]]></category>

		<category><![CDATA[Cloud Computing]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8545</guid>
		<description><![CDATA[By Stacey Higginbotham
Tilera, a startup building chips that contain anywhere from 16 to 100 cores, said today it’s raised $25 million in a third round of funding from investors including Broadcom (BRCM). Chips made by Tilera, which we named as one of five multicore statups to watch two years ago, are aimed at boosting performance [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/cloud-chip/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Intel to Launch Eight-core Nehalem-EX This Month</title>
		<link>http://www.multicoreinfo.com/2010/03/intel-eight/</link>
		<comments>http://www.multicoreinfo.com/2010/03/intel-eight/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 01:09:18 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8543</guid>
		<description><![CDATA[by Agam Shah
Intel will release its fastest and highly anticipated eight-core Nehalem-EX server processor later this month, a company executive said late Thursday.
The processor will be targeted at four-socket servers, said Shannon Poulin, Xeon platform director at Intel. Each physical core will be able to run two threads simultaneously, giving the chip 64 virtual processing [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/intel-eight/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Decompiling the ARM architecture code</title>
		<link>http://www.multicoreinfo.com/2010/03/decompiling/</link>
		<comments>http://www.multicoreinfo.com/2010/03/decompiling/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 01:07:57 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8541</guid>
		<description><![CDATA[At UBM TechInsights, we&#8217;re often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. An embedded algorithm can range from a sensoring technique in an appliance, to motor control, to power management scheme, to navigation algorithm, to UI control or file system on a higher end embedded device; [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/decompiling/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Machine-learning revolutionises software development</title>
		<link>http://www.multicoreinfo.com/2010/03/milepost/</link>
		<comments>http://www.multicoreinfo.com/2010/03/milepost/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 01:00:25 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8539</guid>
		<description><![CDATA[Application developers for software on mobile phones and other embedded devices can achieve acceptable performance levels ten times faster thanks to a breakthrough by European researchers.
Human-readable software code needs to be translated into binary code by a compiler if it is to run on hardware. When hardware is upgraded the software’s compiler usually needs to [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/milepost/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Broadcom takes stake in multicore pioneer Tilera</title>
		<link>http://www.multicoreinfo.com/2010/03/broadcom-tilera/</link>
		<comments>http://www.multicoreinfo.com/2010/03/broadcom-tilera/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 00:58:32 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8537</guid>
		<description><![CDATA[Broadcom Corp. (Irvine Calif.) has made an investment in multicore processor developer Tilera Corp. (San Jose, Calif.). Neither the amount of money invested, nor the percentage size of Broadcom&#8217;s stake, were disclosed, but Tilera has appointed Nariman Yousefi, senior vice president of infrastructure technologies at Broadcom, to the Tilera board of directors.
Tilera&#8217;s processors are based [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/broadcom-tilera/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Processor packs L2 cache for improved performance</title>
		<link>http://www.multicoreinfo.com/2010/03/processor-l2/</link>
		<comments>http://www.multicoreinfo.com/2010/03/processor-l2/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 00:57:46 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8535</guid>
		<description><![CDATA[eASIC Corp. has released the Aeroflex Gaisler&#8217;s LEON4 processor, as part of its eZ-IP Alliance Core Library. LEON4 is a high-performance, 32bit processor core based on the SPARC V8 architecture. The new LEON4 core complements the LEON3 processor for high-performance embedded applications across a broad spectrum of demanding consumer and industrial applications.
The power- and size-optimized [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/processor-l2/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Tilera Raises $25 Million</title>
		<link>http://www.multicoreinfo.com/2010/03/tilera-25mil/</link>
		<comments>http://www.multicoreinfo.com/2010/03/tilera-25mil/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 00:56:37 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8533</guid>
		<description><![CDATA[Tilera® Corporation, developer of breakthrough high-performance TILE™ family of multicore processors, today announced that is has closed out a $25 million series-C of investment financing. The round was oversubscribed and included funds from three new strategic investors: Broadcom Corporation, Quanta Computer and NTT Financing Corp.
“We have grown revenues, design wins, and market momentum in one [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/tilera-25mil/feed/</wfw:commentRss>
		</item>
		<item>
		<title>MathWorks expands tools for multicore and embedded Linux</title>
		<link>http://www.multicoreinfo.com/2010/03/mathworks/</link>
		<comments>http://www.multicoreinfo.com/2010/03/mathworks/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 00:55:22 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8531</guid>
		<description><![CDATA[by Richard Wilson
The MathWorks has announced the latest release of its MATLAB and Simulink product families, which include new streaming capabilities for signal processing and video processing in MATLAB and nonlinear solvers for standard and large-scale optimisation.
Release 2010a also introduces Simulink PLC Coder, which helps industrial control system engineers generate IEC 61131 structured text. This [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/mathworks/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Multicore Madness in 2010</title>
		<link>http://www.multicoreinfo.com/2010/03/multicore-2010/</link>
		<comments>http://www.multicoreinfo.com/2010/03/multicore-2010/#comments</comments>
		<pubDate>Sat, 06 Mar 2010 11:56:49 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8529</guid>
		<description><![CDATA[By Matthew Dublin
From all accounts, 2010 looks to be the year of the multicore processor, but does this finally mean the emergence of HPC at the desk side or just really expensive space heaters that you can Tweet with? Despite a delayed rollout in 2009, Intel is planning on releasing a 6 core processor code [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/multicore-2010/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Intel: What&#8217;s Next for Nehalem</title>
		<link>http://www.multicoreinfo.com/2010/03/next-nehalem/</link>
		<comments>http://www.multicoreinfo.com/2010/03/next-nehalem/#comments</comments>
		<pubDate>Sat, 06 Mar 2010 11:55:21 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8527</guid>
		<description><![CDATA[Intel is pepping to release its “fastest and highly anticipated” eight-core Nehalem-EX server processor later this month, according to reporters familiar with the matter. The processor will be targeted at four-socket servers, Shannon Poulin, Xeon platform director at Intel, told reporters. Additionally, each physical core will be able to run two threads simultaneously, giving the [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/next-nehalem/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Intel Guide for Developing Multithreaded Applications</title>
		<link>http://www.multicoreinfo.com/2010/03/intel-guide/</link>
		<comments>http://www.multicoreinfo.com/2010/03/intel-guide/#comments</comments>
		<pubDate>Fri, 05 Mar 2010 02:05:22 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8525</guid>
		<description><![CDATA[On March 9, 2010 The Parallel Programming Community on the Intel Software Network will be publishing a collection of technical papers to provide software developers with the most current technical information on Application Threading, Synchronization, Memory Management and Programming Tools. Prior to the date of publication we be releasing a few sample papers along with [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/intel-guide/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Detecting Memory Bandwidth Saturation in Threaded Applications</title>
		<link>http://www.multicoreinfo.com/2010/03/bandwidth-sat/</link>
		<comments>http://www.multicoreinfo.com/2010/03/bandwidth-sat/#comments</comments>
		<pubDate>Fri, 05 Mar 2010 02:03:44 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8523</guid>
		<description><![CDATA[Memory sub-system components contribute significantly to the performance characteristics of an application. As an increasing number of threads or processes share the limited resources of cache capacity and memory bandwidth, the scalability of a threaded application can become constrained. Memory-intensive threaded applications can suffer from memory bandwidth saturation as more threads are introduced. In such [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/bandwidth-sat/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Lock free message passing algorithms with Groovy++</title>
		<link>http://www.multicoreinfo.com/2010/03/lock-free-mp/</link>
		<comments>http://www.multicoreinfo.com/2010/03/lock-free-mp/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 23:57:34 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8521</guid>
		<description><![CDATA[by Alex Tkachman
&#8220;Fast immutable persistent functional queues for concurrency with Groovy&#8221; talks about implementation of functional queues with Groovy++. Here is another article to use these queues to implement several algorithms for processing of asynchronious messages. You can find source code and more examples in the Groovy++ distro.
This article discusses implementing simplified actor, the object [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/lock-free-mp/feed/</wfw:commentRss>
		</item>
		<item>
		<title>How do OpenMP Compilers Work? - Part 1</title>
		<link>http://www.multicoreinfo.com/2010/03/openmp-1/</link>
		<comments>http://www.multicoreinfo.com/2010/03/openmp-1/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 23:45:18 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8519</guid>
		<description><![CDATA[by Michael Klemm
We all know that OpenMP is a well-known, widely accepted programming model for parallel programming on shared-memory platforms. It is based on so-called OpenMP directives that programmers add to their code to inform the compiler about which fragments of the program can be executed in parallel. Most of OpenMP is designed to allow [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/openmp-1/feed/</wfw:commentRss>
		</item>
		<item>
		<title>The A4 and the A8: secrets of the iPad&#8217;s brain</title>
		<link>http://www.multicoreinfo.com/2010/03/ipads-brain/</link>
		<comments>http://www.multicoreinfo.com/2010/03/ipads-brain/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 23:34:48 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8517</guid>
		<description><![CDATA[By Jon Stokes, Ars Technica
Most companies, when they go to the enormous expense of designing a complex chip, tell everyone about it. Even a company like Sun or IBM, whose chips are used only in their own computers, unveil the details of their new processors well before products based on those new parts come to [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/ipads-brain/feed/</wfw:commentRss>
		</item>
		<item>
		<title>Best Bets in Cloud-Computing Networking</title>
		<link>http://www.multicoreinfo.com/2010/03/best-bets-net/</link>
		<comments>http://www.multicoreinfo.com/2010/03/best-bets-net/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 23:31:01 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[Cloud Computing]]></category>

		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8515</guid>
		<description><![CDATA[ KEY CLOUD-COMPUTING TAKEAWAY: The network is broken.
Pacific Crest hosted seven panels and 30 company presentations on cloud-computing trends at the Fourth Annual Emerging Technology Summit in San Francisco last week. Despite the perception of the cloud as overhyped, it was clear that most, if not all, hardware, software and services companies are aggressively repositioning [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/best-bets-net/feed/</wfw:commentRss>
		</item>
		<item>
		<title>POWER, Itanium, Niagara: Superscalar vs. VLIW vs. Simple Multicore</title>
		<link>http://www.multicoreinfo.com/2010/03/power-itanium-niagara/</link>
		<comments>http://www.multicoreinfo.com/2010/03/power-itanium-niagara/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 23:27:05 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8513</guid>
		<description><![CDATA[by Greg Pfister
The recent near-simultaneous announcements of IBM&#8217;s POWER7 and Intel&#8217;s Itanium 9300 (&#8221;Tukwila&#8221;) invites some background on how those differ in essential architecture, why VLIW (Itaniam&#8217;s architecture) never was a good idea in the first place, and how they compare to the alternative simple multicore systems such as Sun&#8217;s (now Oracle&#8217;s) Niagara. 
Why do [...]]]></description>
		<wfw:commentRss>http://www.multicoreinfo.com/2010/03/power-itanium-niagara/feed/</wfw:commentRss>
		</item>
		<item>
		<title>IBM jumps &#8216;last hurdle&#8217; to on-chip optical communication</title>
		<link>http://www.multicoreinfo.com/2010/03/optical-comm-ibm/</link>
		<comments>http://www.multicoreinfo.com/2010/03/optical-comm-ibm/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 23:25:46 +0000</pubDate>
		<dc:creator>Sujana</dc:creator>
		
		<category><![CDATA[MulticoreInfo]]></category>

		<guid isPermaLink="false">http://www.multicoreinfo.com/?p=8511</guid>
		<description><![CDATA[IBM Research claimed a keystone achievement in on-chip optical communications Wednesday (March 3), saying its 40-gigabit-per-second (Gbps) germanium avalanche photodetector completes what it calls the nanophotonic toolkit.
Capping its multi-year effort by surmounting this final technological hurdle, IBM (Yorktown Heights, N.Y.) now claims to have all the pieces to enable chip-to-chip optical communications and ultimately core-to-core [...]]]></description>
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