by Evgueni Brevnov, Max Domeika, et al., Intel Corporation
This article describes the evolution, implementation, usage, and performance evaluation of a bi-endian capable compiler. Software migration of legacy applications from one endian architecture to another is often hampered [...]

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The U.S. Department of Energy announced today that proposals are now being accepted for the Innovative and Novel Computational Impact on Theory and Experiment (INCITE) program.
The U.S. Department of Energy announced today that proposals are now being accepted for the Innovative and Novel Computational Impact on Theory and Experiment (INCITE) program, which supports high-impact scientific [...]

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by Aaron Spear, VMware
Modern multi-core designs often aggregate wildly different hardware and software technologies. Traditional debuggers, which show a snapshot of a portion of the system, do little to uncover issues that arise due to complex interaction of components.
Engineers routinely cobble together proprietary tracing facilities in order to have some chance of catching [...]

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The II Open Source Software, Multicore and Parallel Computing Miniconference, part of LCA2011 was held in Brisbane, Australia on Tuesday 25 of January 2011. Here is a list of interesting presentations at the miniconference. Vint Cerf (VP of Google and “Father of the Internet”), Linus Torvalds (Linux kernel Project Coordinator), and Paul McKenney (IBM’s Linux [...]

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# Intel Labs announced $100 million cash investment in U.S. university research over the next 5 years, marking a new model of collaboration for the organization.
# Funding will support a number of Intel Science and Technology Centers; the first such center will be led by Stanford University and focus on next-generation visual computing.
# This new [...]

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The European Exascale Software Initiative (EESI) is formed with the goal of building a European vision and roadmap to address the challenge of the new generation of massively parallel systems composed of millions of heterogeneous cores which will provide Petaflop performances in 2010 and Exaflop performances in 2020.

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American computer researchers say they have developed new software which makes programming of multi-processor machines much easier.
“With older, single-processor systems, computers behave exactly the same way as long as you give the same commands. Today’s computers are non-deterministic,” says Luis Ceze, computer science and engineering prof at the University of Washington, Washington. “Even if you [...]

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The 16th International Symposium on High-Performance Computer Architecture (HPCA) and 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010) were held in Bangalore, India between January 9th and 14th. These are two premier conferences covering research in a wide range of topics in high-performance computer architecture and parallel programming.
There [...]

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By Ryan Paul
The USPTO awarded search giant Google a software method patent that covers the principle of distributed MapReduce, a strategy for parallel processing that is used by the search giant. If Google chooses to aggressively enforce the patent, it could have significant implications for some open source software projects that use the technique, including [...]

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CAPS, a leading global provider of compiler technologies and engineering services for parallel hybrid
computing, has announced that Oak Ridge National Laboratory (ORNL) will use CAPS’ HMPP
compiler to leverage the computing power of a graphics processing unit (GPU)-based hybrid cluster.
As a world leader in high-performance computing (HPC), ORNL is preparing the future of next-
generation petascale computing [...]

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By Nicolas Mokhoff
“Semiconductor research is coming up short on new ideas to extend Moore’s Law of consistently packing more transistors on a chip. Innovations in emerging technologies need to be accelerated.
That was Pushkar Apte’s claim at the International Electron Devices Meeting here as some 1200 researchers gathered to present and take in the latest technology [...]

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As part of a company-wide goal of reaching sustained exascale performance by the end of the next decade, global supercomputer leader Cray Inc. (NASDAQ: CRAY) today announced the launch of its Exascale Research Initiative at the Cray Executive Forum Europe currently taking place in Frankfurt, Germany. This research initiative will explore new ideas and technologies [...]

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Despite all the all the recent hoopla about GPGPUs and eight-core CPUs, proponents of reconfigurable computing continue to sing the praises of FPGA-based HPC. The main advantage of reconfigurable computing, or RC for short, is that programmers are able to change the circuitry of the chip on the fly. Thus, in theory, the hardware can [...]

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The biennial ACM Symposium on Operating Systems Principles (SOSP) was held between Oct 11th and 14th, in Big Sky, MT. It is one of the world’s premier forums for researchers, developers, programmers, vendors and teachers of operating system technology.
42nd International Symposium on Microarchitecture (MICRO-42) will be held in Newyork, NY from December 12th to 16th. [...]

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by Charles Leiserson
When multicore-enabling a C/C++ application, it’s common to discover that malloc() (or new) is a bottleneck that limits the speedup your parallelized application can obtain. This article explains the four basic problems that a good parallel storage allocator solves:
* Thread safety
* Overhead
[...]

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University researchers have proposed a new power management technique that they say significantly reduces energy consumption without negatively impacting the reliability of the system. The scheme, dubbed shared recovery technique, was the subject of a paper presented at the International Conference on Computer-Aided Design (ICCAD) Monday (Nov. 2) by Baoxian Zhao, a computer science graduate [...]

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By Lucas Mearian
Engineers have created a new fingernail-size chip that can hold 1 trillion bytes (a terabyte) of data — 50 times the capacity of today’s best silicon-based chip technologies.
The engineers, from North Carolina State University, said their nanostructured Ni-MgO system can store up to 20 high-definition DVDs or 250 million pages of text, “far [...]

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Researchers at Carnegie Mellon University and Intel Labs Pittsburgh (ILP) have combined low-power, embedded processors typically used in netbooks with flash memory to create a server architecture that is fast, but far more energy efficient for data-intensive applications than the systems now used by major Internet services.
An experimental computing cluster based on this so-called Fast [...]

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A $5.5 million contract has been awarded by the US Defense Advanced Research Projects Agency (DARPA) to Raytheon to design, fabricate and test self-healing mixed-signal ics.
The HEALICS contract, as it is known, could be worth $11million for Raytheon if both project phases are completed. Phase one involves the demonstration of a self-healing mixed-signal core; and [...]

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Professor Pierre Boulanger at University of Alberta is offering a course on Programming multicore architectures. MulticoreInfo is honored to be a part of class resources of this course.
From the Professor’s website, the course description is as follows:
“This course is intended to give students an understanding of multi-core architectures and parallel programming models. Student will [...]

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