The National Center for Supercomputing Applications (NCSA) will offer a free webinar on Getting Started with Performance Tools from 1:30 to 3 p.m. CST on Thursday, Feb. 25.
This webinar, led by NCSA system engineer Galen Arnold, will provide an introduction to performance tools and techniques. A common application, High Performance Linpack (HPL), will be analyzed [...]

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By Max Domeika
As a follow-on to Part 1, which included, among other things, an overview of compiler optimization as it relates to parallelization of code for multicore applications, in this second part in this series, the discussion will detail a process for applying these optimizations to your application.
This process consists of four steps:
1. Characterize the [...]

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by Michael Feldman, HPCwire Editor
“I’m riding a train to San Francisco, and I’m reading a newspaper. The train’s vibrating and my arms are vibrating and the newspaper’s vibrating. I can still read the newspaper, but it takes more concentration, so I don’t read as fast as I normally do. It’s just more work to [...]

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Acceleware® Corp., a leading developer of high performance computing applications, today announced a partnership with Crosslight Software to deliver acceleration for thin-film solar cell and image pixel sensor simulations. APSYS™, Crosslight’s 2/3D electrical and electromagnetics simulation tool for semiconductor design, combined with Acceleware’s acceleration solution for the finite difference time domain (FDTD) algorithm now delivers [...]

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by Johan De Gelas
Performance per Watt rules the datacenter, right? Wrong. Yes, you would easily be lead astray after the endless “Green ICT” conferences, the many power limited datacenters, and the flood of new technologies that all have the “Performance/Watt” stamp. But if performance per Watt is all that counts, we would be all be [...]

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by David Mackay
Libraries play an important role in threading software to run faster on Intel multi-core platforms.
Multi-core platforms are the default computer platforms sold throughout the world. On a multi-core platform there are multiple processors contained on a single chip. That is, each chip has multiple cores that are each [...]

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by Victor J. Duvanenko
Algorithm Improvement through Performance Measurement: Part 1
Algorithm Improvement through Performance Measurement: Part 2
Algorithm Improvement through Performance Measurement: Part 3
The In-place Hybrid MSD N-bit-Radix Sort I presented in In-place Hybrid N-bit-Radix Sort was developed as a combination of Radix Sort, Insertion Sort, and Counting Sort. This algorithm sorts arrays of integers [...]

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By John Blyler
Here is an interview with Max Domeika, senior software engineer in the Developer Products Division at Intel, by Low Power Engineering’s John Blyler to talk about the growing importance – and intersection – of both the multicore and embedded markets.
How do these processor states affect the development of software applications?
In the past, processors [...]

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AccelerEyes is pleased to announce the release of the HPC industry’s first GPU performance benchmark: Jacket GBENCH. GBENCH allows users to gauge the GPU performance of their computer relative to equivalent benchmarks obtained from a variety f other computers, including the CPU of the same computer. Benchmarks include six different tasks, common to [...]

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By James Reinders (Intel)
Available today: a way to test scaling using cloud-computing, Intel has released this web-based tool to help with parallel programming. The Intel® Parallel Universe Portal will take your Windows (32 bit) application, run it through the scaling analysis engine in Intel Parallel Studio, and give back a report about the performance running [...]

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Under the Debugger Software Enhancement program for Petascale production grade tools, awarded to Allinea Software Inc. by Oak Ridge National Laboratory in Q2 2009, Allinea’s Distributed Debugging Tool (DDT) is setting new levels of debugger scalability on Jaguar, a Cray XT5 and one of the world’s largest supercomputers.
In Q2 2009, Allinea began a collaborative project [...]

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by Robert Cravotta, Technical Editor - EDN
Texas Instruments’ new six-core TMS320C6472 DSP boasts a 3.68W power-use sweet spot when operating all six cores at 500 MHz with 80% usage.
The cores support 625- and 700-MHz operation with a trade-off of energy efficiency at the 500-MHz operation point. The device includes 4.8 Mbytes of L1 and L2 [...]

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By Rick Nelson, Editor in Chief — Test & Measurement World
Freescale Semiconductor’s test engineers deliver the data necessary to get the company’s six-core network processors to market.
Freescale Semiconductor is addressing the processing needs of wireless broadband equipment vendors with devices such as its MSC8156, a six-core DSP based on the company’s new SC3850 StarCore technology. [...]

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by Gaston Hillar
It is very important for Windows developers to understand the differences found in the complex underlying multicore and manycore hardware. Coreinfo is a very simple yet powerful command-line utility that shows you very useful information about the processors, their organization and the cache topology. A few days ago, Mark Russinovich, a well-known member [...]

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by Gaston Hillar
Visual Studio 2010 Beta 2 includes many interesting improvements related to its multicore programming features. The parallelism and concurrency profiling tools allow developers to visualize the behavior of a multithreaded application on multicore microprocessors and collect resource contention data.
If you want to translate multicore power into application performance, you have to make sure [...]

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by Andrew Binstock
While much of the kernel that lies at the heart of Windows 7 is based on Vista code, several key advances have been made that get rid of Vista annoyances and greatly improve the user experience.
Inside the kernel, one important change centres on how multithreaded applications are run. The threading advances provide [...]

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Professor Pierre Boulanger at University of Alberta is offering a course on Programming multicore architectures. MulticoreInfo is honored to be a part of class resources of this course.
From the Professor’s website, the course description is as follows:
“This course is intended to give students an understanding of multi-core architectures and parallel programming models. Student will [...]

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by Lerie Kane and Max Domeika
The implementation of parallelism in a system can take many forms; one commonly used type is shared memory parallelism which implies the following:
* Multiple threads execute concurrently.
* The threads share the same address space. This is compared to mu ltiple processes which [...]

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By Max Domeika
One common question when customers review data from microprocessor benchmarks such as those discussed in Part 1 is “How well will benchmark performance predict my particular application’s performance if I employ your new processor or new compiler?”
In other words, if a new processor or different compiler increases the performance of benchmark X by [...]

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By Max Domeika
Determining the specific multi-core processor that will suit your embedded application needs is a challenge. Relying upon the marketing collateral from a given company is not sufficient because in many cases, the results quoted are specific to a given platform and ambiguous application; there is no guarantee your application will exhibit the same [...]

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