IBM Corp. said Wednesday (Sept. 1) that it will begin shipping Sept. 10 a new mainframe computer computer capable of 50 billion instructions per second, powered by 96 microprocessors with clock speeds up to 5.2 gigahertz.
IBM (Armonk, N.Y.) said the z196 processor is a four-core chip that contains 1.4 billion transistors on a 512-square millimeter [...]

[Read more →]

by Anand Lal Shimpi
The mainstream quad-core market has been neglected ever since we got Lynnfield in 2009. Both the high end and low end markets saw a move to 32nm, but if you wanted a mainstream quad-core desktop processor the best you could get was a 45nm Lynnfield from Intel. Even quad-core Xeons [...]

[Read more →]

By Andrew Binstock
It’s been eight years since simultaneous multithreading first appeared in popular processors, when Intel shipped it under the name of Hyper-Threading Technology. Since then, numerous companies have been trying to figure out how to get developers to leverage multiple threads on the desktop, whether in a single CPU or in the now-common multicore [...]

[Read more →]

By Wolfgang Gruener
With the release of the first versions of Chrome 7, we noticed a subtle speed increase in graphics-heavy websites and suggested that Google is improving Chrome’s overall graphics performance. Our readers later found that GPU acceleration can already be manually activated in Chrome. Google has now officially confirmed that “there’s been a [...]

[Read more →]

For this 5-part article, Jim Dempsey takes a small, well-known algorithm, shows a common approach to parallelizing that algorithm, follows with a better one and lastly, produces a fully cache-sensitized approach. Readers will learn a methodology for interpreting test run statistics and to improve their code using those interpretations.
Part 1
Part 2
Part 3
Part 4
Part 5

[Read more →]

The ParBenCCh suite is a collection of small C and C++ applications designed to characterize compiler optimization capabilities, language support, object-oriented-programming style overhead, and machine performance. We have developed a testing framework using a virtual base class that encapsulates the essential functionality of any benchmark. Each of our specific tests derive from this base class [...]

[Read more →]

by Jim Dempsey
This article examines superscalar programming techniques on HyperThread and Shared cache systems.
For background information, see the five-part article series on Superscalar Programming 101 (Matrix). That article series demonstrates superscalar techniques but does not fully demonstrate the relationship between running your HyperThread capable system with HyperThreading disabled verses HyperThreading enabled. This article focuses on [...]

[Read more →]

Graphic Processing Units (GPUs) in High-Performance Computing (HPC), promise the prospect of dramatically increasing HPC performance.
However, as we all know, achieving real-world performance is about much more than just the raw-performance of underlying hardware. Similar to a highly-efficient power plant connected to a distribution network that loses 70% of its power in transmission, HPC GPU [...]

[Read more →]

By Lori Matassa and Max Domeika
The focus of multi-core processor tuning is on the effective use of parallelism
ood software design seeks a balance between simplicity and efficiency. Performance of the application is an aspect of software design; however correctness and stability are typically prerequisite to extensive performance tuning efforts. A typical development cycle is [...]

[Read more →]

By Ann Steffora Mutschler
Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications.
With millions of different embedded products, all with different sets of software, it comes down [...]

[Read more →]

LSU research group part of DARPA project to create advanced computing systems
A research group with LSU’s Center for Computation & Technology (CCT), has received two awards to provide fundamental technical contributions to the recently announced Defense Advanced Research Projects Agency (DARPA) Ubiquitous High Performance Computing Program (UHPC). This program brings together researchers and scientists from [...]

[Read more →]

The term “supercomputing” usually evokes images of large, expensive computer systems that calculate unfathomable algorithms and run on enough energy to support a small city. Now, imagine a supercomputer, but run on the electrical equivalent of three standard-size coffee-makers.
This year’s international supercomputing conference, SC10, will feature the Student Cluster Competition that challenges students to build, [...]

[Read more →]

A chief architect of China’s microprocessor initiative described an ambitious set of new Godson CPUs including a server chip with vector processing. Wei-wu Hu, a professor at Beijing’s Institute of Computing Technology that has led development of the chips, announced several new 65 nm parts debuting in 2011 and plans to leapfrog to a 28-nm [...]

[Read more →]

by Michael Feldman, HPCwire Editor
Now that AMD has jettisoned its chip production business with the Globalfoundries spinoff, it can concentrate on what it has always done best: microprocessor design. Much of its success early in the decade resulted from outmaneuvering Intel, its much larger rival, in the lucrative x86 server space. With the Opteron [...]

[Read more →]

It’s been a long time since the last major AMD microarchitecture refresh, and in the meantime, Intel’s handily won the performance crown. The second-place chipmaker hasn’t spent its time idly, working instead on their first entirely-new x86 chips in close to a decade.
For AMD, Bulldozer and Bobcat are the future. Are they right?
As the [...]

[Read more →]

by Gaston Hillar
When you write concurrent code that has to make changes to shared variables, you might think that a mutual-exclusion lock is necessary to perform each update operation. In some cases, you can replace a mutual-exclusion lock with a more efficient atomic operation and you can boost both your application’s performance and scalability.
When you [...]

[Read more →]

Two Easy Steps to Better Performance
Step 1. Find the hotspot(s): Measure where the application is spending time
In order to tune effectively, you must optimize the parts of the applications that demand a lot of time. Tune something that is already fast, and you will see very little benefit. A “hotspot” is a place where
the app [...]

[Read more →]

Intel on Monday introduced its second dual-core Atom processor, and announced that more than a half dozen computer makers have signed on to ship netbooks with the latest low-power chip.
The 1.5 GHz N550 is built on the Pine Trail Atom platform, introduced last year, and is a higher-performing alternative to the single-core N450 used in [...]

[Read more →]

by Rick Merritt
Advanced Micro Devices will make its first public presentations on Bulldozer and Bobcat today (Aug. 24), its first new x86 cores designed from a clean sheet of paper in ten years. The cores will form the underpinning of most of the products AMD will build over the next five to ten years to [...]

[Read more →]

by Lloyd Dickman
High-performance computing users invest in performance-oriented interconnect fabrics such as InfiniBand to provide adequate system balance to match the computational capabilities of modern multi-core processors and GPUs. However, as HPC system sizes continue to grow with at least hundreds of nodes, thousands of cores and numerous simultaneous jobs, users are increasingly sensitive [...]

[Read more →]