The semiconductor memory industry is about to experience major technological changes as three-dimensional multi-gate structures push transistors and memory architectures forward, according to a one-day memory workshop held last month in Grenoble, France, by leading researchers from around the world.
Traditionally, CMOS downscaling has had the double benefit of increasing device performances and reducing power consumption. [...]

[Read more →]

Attach a couple of cobalt molecules to a ring of carbon and you have the dream memory material. There’s a challenge facing electronics engineers attempting to build magnetic memory that can store data for more than 10 years or so. The density at which this data is stored depends on the size of the [...]

[Read more →]

Rambus, a technology licensing companies specialising in high-speed memory architectures, has demonstrated its XDR memory system running at data rates up to 7.2 Gbps. The demonstration comprised memory-manufacturer Elpida’s recently announced 1 Gbit XDR DRAM device and an XIO memory controller transmitting realistic data patterns.
Elpida claims the XIO memory controller is up to 3.5 times [...]

[Read more →]

Following an active panel on DDR3 DRAM, last week’s Denali Memcon offered up a second panel topic: low-power memory design. That’s a wide enough topic to allow for a range of discussions, and the panelists–Mostafa Abdulla of Numonyx, Roger Isaac of Silicon Image, Areski Maklouf from ST-Ericsson, and Howard Sussman of Etron—ranged all over it.
In [...]

[Read more →]

by Douglas Eadline
“Basically, it does not matter how many cores you have if you cannot keep them busy. There are limits to how fast memory can transmit data to and from cores. The placement of memory controllers on the processor allows parallel (simultaneous) memory access on an SMP motherboard. That is, instead of one memory [...]

[Read more →]

Rambus has demonstrated an XDR memory system capable of achieving data rates of up to 7.2Gbps. The system - showcased at the 2009 Denali MemCon - was comprised of Elpida’s 1Gb XDR DRAM device, along with an XIO memory controller designed to transmit realistic data patterns. The XIO memory controller also demonstrated bi-modal operation with [...]

[Read more →]

RNA networks, the leader in memory virtualization software, today announced it has extended its Memory Virtualization Platform (MVP) product family with the release of RNAcache. MVP transforms server memory into a shared network resource. RNAcache allows servers to leverage RNA’s unlimited pool of memory by loading entire working datasets into a single shared, virtual [...]

[Read more →]

When it comes to data storage, density and durability have always moved in opposite directions — the greater the density the shorter the durability. For example, information carved in stone is not dense but can last thousands of years, whereas today’s silicon memory chips can hold their information for only a few decades. Researchers with [...]

[Read more →]

Chip design services provider eInfochips has unveiled a memory model generator based on the DDR2 SDRAM SystemVerilog Verification Methodology Manual approach.The tool will generate behavioral models for leading memory vendors including Elpida, Hynix, Micron and Samsung. The tool is designed to reduce the time needed for verification while maximizing memory coverage, the company claims.
The [...]

[Read more →]

By John Nieto, Inphi Corp for EDN
Applications demanding higher system bandwidth and lower power, such as converged notebooks, desktop PCs, and servers, continue to drive the evolution of industry standards, including DDR3 (double-data-rate 3), as the JEDEC (Joint Electron Device Engineering Council) Solid State Technology Association defines it. The latest DDR3-memory standard, JEDEC JESD79-3A, supports [...]

[Read more →]

Rambus Inc., one of the world’s premier technology licensing companies specializing in high-speed memory architectures, today unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps. These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies. Through this collection [...]

[Read more →]

Rambus has announced a set of new and existing interconnect technologies it says will meet the needs of main memory in 2011 and beyond. It hopes the industry adopts the techniques as part of a pending DDR4 DRAM standard.
The concepts are promising, but a history of intellectual property disputes clouds the road to adopting them. [...]

[Read more →]

In many embedded systems applications, developers are often caught on the horns of a dilemma. On the one hand, they are constrained to use the limited memory space available as efficiently as possible. But at the same time, they are required to get as much performance out of the hardware resources (including memory) as is [...]

[Read more →]

Nehalem brings a new memory architecture to the Intel processor lineup. Rather than have the memory controller located off the CPU (remember the Front-Side Bus, FSB, architecture?) the memory controller is now on the CPU! In addition, there are up to three memory channels that are connected to each socket and up to three DIMMs [...]

[Read more →]

Sonics, Inc., a premier supplier of intelligent on-chip communications solutions, has announced the availability of the MemMax Memory Scheduler 3.0, a DRAM access scheduler ideally designed for use with DDR2 and DDR3. Targeted at SoCs requiring high-bandwidth traffic management to the memory subsystem, the new MemMax Scheduler accelerates on-chip performance while easing design integration. MemMax [...]

[Read more →]

For design engineers developing the next generation motherboards, DRAM memory is becoming a major concern as end-users demand more memory. Software operating systems are getting larger and the applications are demanding more RAM than ever before.
New technologies, such as server virtualization, multi-core processor chips and dense blade servers have all increased the demand for memory. [...]

[Read more →]

by Erik Hagersten, CTO of Acumem. Source: HPCWire
“Trading Parallelism for Performance
It is a common belief that only sequential applications need to be adapted for parallel execution on multicore processors. However, many existing parallel algorithms are also a poor fit. They have simply been optimized for the wrong design parameters.
In the past we have been striving [...]

[Read more →]

After analyzing state-of-the-art DRAM devices from the Korean manufacturers Samsung and Hynix, Semiconductor Insights gave Micron its turn under the magnifying glass. With the help of advanced imaging techniques, SI analyzed the process technology used to fabricate Micron’s newest 1-Gbit DDR2 50-nm SDRAM and is now ready to reveal some of the design trends introduced [...]

[Read more →]

Google Tech Talks has a video of Mark D. Hill (http://www.cs.wisc.edu/~markhill) discussing his corollary to Amdahl’s Law for multicore chips [Hill & Marty, IEEE Computer 2008]. It models fixed chip resources for alternative designs that use symmetric cores, asymmetric cores, or dynamic techniques that allow cores to work together on sequential execution.

At the end [...]

[Read more →]

outh Korea’s Samsung Electronics Co. Ltd. said Thursday (March 19) it shipped the first high-density memory modules based on 2-gigabit (Gb), 50-nanometer-class DDR3 memory.
Samsung (Seoul) said it is shipping 18 configurations of its high-density DDR3-based modules, designed for servers. The modules include a 16-gigabyte (GB) registered inline memory module and an 8-GB registered dual inline [...]

[Read more →]