By Tom Simonite, MIT Technology Review
Researchers at the University of California, Santa Barbara, have become the first to combine a quantum processor with memory that can be used to store instructions and data. This achievement in quantum computing replicates a similar milestone in conventional computer design from the 1940s.

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by Jared Bell, AnandTech
Investigating Sandy Bridge Memory ScalingFull Story

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by Shameem Akhter, Jason Roberts, and Andrew Binstock
For multithreaded software to run optimally, developers must understand subtle aspects of memory access
Parallel programming is gaining favor as the multicore architecture becomes ubiquitous. On processors based on the x86 architecture, running threads in parallel presents memory problems beyond the typical concerns of keeping threads from interfering with [...]

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ISC 2011 paper titled “Experiments with the Fresh Breeze Tree-Based Memory Model” authored by Jack Dennis (MIT), Guang R. Gao, and Xiaoxuan Meng (Univ. of Delaware), won the prestigious Gauss Award.
Here is the abstract:
The Fresh Breeze memory model and system architecture is proposed as an approach to achieving significant improvements by supporting fine-grain management [...]

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by Shameem Akhter and Jason Roberts, Intel Corporation
Abstract
When programming for multiple thread or multiple core systems, it is important to realize the fundamental difference in memory allocation and access necessary from that of a single thread or core system. Contention and sharing with respect to memory locations can severely reduce the speedup gained from programming [...]

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by Ganesh Balakrishnan et al.
In this paper, the authors examine the architecture and performance of the Intel® Xeon® processor 5600 Series. Similar to the 5500 Series processors, the 5600 architecture will also present challenges to customers due to the flexibility and configuration choices offered by the new platform. The performance analysis will cover latency to [...]

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LSI Corp. has added a new Power PC processor and fast embedded DRAM cores to its library, claiming demand for custom silicon is on the rise in its core networking and storage markets. The company also is leveraging a 10 Gbit Ethernet core licensed from startup Teranetics and 40 and 28nm process technology from foundry [...]

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by Mary Jo Foley
“When Microsoft released Visual Studio 2010 Beta 2 in October, company officials said it was looking likely that the product would ship on or around March 22, 2010. But due to some feedback from testers around virtual memory performance, Microsoft is delaying the launch by “a few weeks.”
Senior Vice President of Microsoft’s [...]

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by Jake McTigue
The first part of this series talks a great deal about native support for NUMA in vSphere on enabled Opteron and Nehalem processor platforms. NUMA is a strong technology in and of itself, but it really starts to shine when teamed with other supporting technologies. This post covers the details of integrating next [...]

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DDR memory technology is the most common choice of memory devices found almost everywhere from computers, transportations, home entertainment systems to medical devices and consumer products. With the wide spread of the DDR usage, the new development and designs are pushing the requirement for higher performance and more power-efficient DDR memory devices.
New DDR technologies such [...]

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By Timothy Prickett Morgan
Everybody is looking to shake up the server business this days, it seems. But everyone had better get in line behind 3Leaf Systems, which is launching its much awaited “Aqua” system pooling and virtualization chipset and an intriguing x64 system to match.
A little more than two years ago, 3Leaf Systems came out [...]

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Micron Technologies Inc. has introduced a multi-chip package (MCP) memory for smart phones, personal media players, and mobile Internet devices (MIDs) that includes a 4-Gbit NAND flash memory die and a 2-Gbit low-power DDR die.
The 4-Gbit NAND flash memory is implemented in 34-nm process technology while the DRAM is implemented in a 50-nm process. The [...]

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At SC09, the 22nd annual Supercomputing Conference, Inphi will launch its Isolation Memory Buffer, the industry`s first component based on Inphi`s innovative Isolation Memory Buffer (iMB) technology. The iMB memory architecture enables servers to take full advantage of multicore and virtualization technologies. Inphi`s iMB component is driving the creation of LR-DIMMs, a new class of [...]

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By Richard Adhikari
Intel and Numonyx, a company created by Intel and STMicro, say they’ve recently made significant headway in the development of phase change memory. PCM is a type of non-volatile computer memory, which means it does not require a constant power supply to retain information. Though the new developments aren’t ready for products yet, [...]

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by Stephen Shankland
Wondering why your computer just crashed again? Its memory might be to blame, according to real-world Google research that finds error rates higher than what earlier work showed.
With hundreds of thousands of computers in its data centers, Google can collect an abundance of real-world data about how those machines actually work. That’s [...]

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Rambus Presentation
Tuesday, September 22, 11:15 a.m. PDT
“Memory Architectures for Multi-core Computing in Next-generation PCs and Smartphones”
Presented by Craig Hampel, Rambus Fellow
Moscone Center West, Room 2005
Mr. Hampel will address memory architecture optimizations that can support the many threads and workloads handled by multi-core processors in next-generation PCs and Smartphones. As part of his talk, Mr. Hampel [...]

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The collaborative development of a threaded module prototype using DDR3 DRAM technology has been announced by Rambus, one of the world’s premier technology licensing companies specializing in high-speed memory architectures, and Kingston Technology, a independent world leader in memory products, today announced. Initial silicon results show an improvement in data throughput of up to 50 [...]

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Rambus and Kingston Technology are collaborating on the development of a threaded module prototype using DDR3 DRAM technology. According to the companies, initial results show data throughput can be boosed by up to 50%, with a 20% reduction in power consumption.
“As multicore computing becomes pervasive, DRAM subsystems will be severely challenged to deliver the data [...]

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by Michael Feldman, HPCwire Editor
GPUs are becoming more like CPUs. But in the critical area of error corrected memory, graphics hardware still lags. The lack of error correction is probably the single biggest factor that makes users of GPUs for high performance computing nervous. Some HPC applications are resistant to the occasional bad data value, [...]

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For over a decade, materials researchers have sought a ferroelectric material that could work in flash-sized bit cells that retain information for as long as a decade–the base requirement for nonvolatile memories.
Researchers at Yale University and the Semiconductor Research Corp. (SRC) claim that ferroelectrics are more appropriate for replacing DRAM than flash. Current DRAM technology [...]

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