By Pallab Chatterjee
The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts. That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and [...]

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The addition of multiple cores to microprocessors has created a significant opportunity for parallel programming, but a killer application is needed to push the concept into the mainstream, researchers said during a panel discussion at the Hot Chips conference.
The addition of multiple cores to microprocessors has created a significant opportunity for parallel programming, but a [...]

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by Michael Feldman, HPCwire
The latest and greatest chippery was on exhibit earlier this week at the Hot Chips conference, an IEEE-sponsored event that encourages microprocessor vendors to talk about their next generation silicon. The emphasis is on high performance chips, so a lot of the products and technology presented at the conference eventually end up [...]

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NVIDIA Corporation today announced that it will be working with TopCoder, a competitive software development community, on the CUDA Superhero Challenge, a series of contests for computer programmers who will harness the parallel processing power of the NVIDIA® CUDA™ architecture to solve some of computing’s biggest challenges.
The first contest, which is open to all eligible [...]

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The Intel® Threading Challenge attracts some of the most talented developers in the world to solve parallel coding challenges. Now is your chance to take multithreading to the next level, demonstrate your threading expertise, and possibly win prizes.
PROBLEM 1 OF PHASE 2 IS NOW OPEN! You will have until September 11, 2009 to submit [...]

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The Center for Information Services and High Performance Computing Dresden (ZIH) announces the 3rd Parallel Tools Workshop, which is organized jointly with the High Performance Computing Center Stuttgart (HLRS). The event will be held on September 14th and 15th.
According to the website, talks and exercises will focus on state-of-the-art tools in the field of [...]

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At the end of this month Hot Chips XXI will be held at Stanford University in Palo Alto. Hot Chips is a relatively unique conference, focused on microprocessors and related topics, with an emphasis on industry and a presence from academia. The program for Hot Chips XXI was put out in early June, and has [...]

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Graduate students — from various disciplines and institutions across the country — are improving their multicore programming skills this week during a summer school course offered by the Great Lakes Consortium’s Virtual School of Computational Science and Engineering.
High-definition streaming video enables students to participate in the course, “Many-Core Programming for Science and Engineering Applications,” from [...]

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Webinar: Tue, Aug 25, 2009 9:00 AM - 10:00 AM PDT
The Presenters: Max Domeika (Intel) and David Stewart (CEO and co-founder of CriticalBlue)

While the industry and academics toil away on long term research into languages and methodologies, the practical side of the industry has an immediate need to better understand how today’s C/C++ code can [...]

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Webinar: Tuesday, August 11, 2009 9:00 AM - 10:00 AM PDT
The Presenter: Jim Holt

Managing application layer shared resources on a multicore chip requires features that include synchronization primitives and memory allocation and management. Most OSs provide rich resource management features, but many multicore programmers must work within systems that use multiple OSs because the cores [...]

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“CoreMark is a simple, yet sophisticated, benchmark that is designed specifically to test the functionality of a processor core. Running CoreMark produces a single-number score allowing users to make quick comparisons between processors. In this webinar, Shay will start off with an introduction to the CoreMark basics, including a description of the benchmark’s functional composition, [...]

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By Richard Goering
“The Wednesday keynote speech at the Design Automation Conference offered a strong argument for general-purpose graphical processing units (GPGPUs) as the best way to accelerate EDA and other compute-intensive applications. But whether GPGPUs will prove to be a better solution than more conventional multicore architectures is a difficult question to answer.
The speaker was [...]

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As has been the case for the past several years, low-power design is expected to be one of the central themes of the 46th Design Automation Conference (DAC).
Power, arguably today’s No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks. An unknown number of products will be introduced [...]

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The Intel Academic Community announced the launch of its center of excellence for faculty training at M S Ramaiah Institute of Technology (MSRIT), Bangalore, India.
This Center of Excellence at the MSRIT campus which is fully equipped with latest Intel hardware and software aims to train 300 faculties from 155 institutes of Visveswaraiah Technological University (VTU) [...]

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Managing application layer shared resources on a multicore chip requires features that include synchronization primitives and memory allocation and management. Most OSs provide rich resource management features, but many multicore programmers must work within systems that use multiple OSs because the cores have different instruction sets, because the memory is not uniformly accessible by all [...]

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Cilk Arts teamed up with MIT’s Professional Development Program on a 2-day workshop focused on multicore programming. Here is the video of second day’s lecture.
The second lecture covered:
* What is Parallelism?
* Scheduling Theory
* Cilk++ Runtime System
* A Chess Lesson

Source
Slides

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Cilk Arts recently teamed up with MIT’s Professional Development Program on a 2-day workshop focused on multicore programming.
The first lecture covered:
* The multicore programming challenge
* Shared-memory hardware
* Leading concurrency platforms (Pthreads, OpenMP, TBB, Cilk++)
* Race conditions

Source

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eXludus Technologies, the leading developer of multi-core system capacity management, virtualization and provisioning solutions, today announced that it will be part of a team of electronic design automation (EDA) and cloud computing experts to offer a free workshop during the Design Automation Conference 2009 (DAC09) in San Francisco.
This workshop will be held on July [...]

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Jeff Vetter from Oak Ridge National Labs sent a message regarding the final report of exascale interconnection networks workshop that was held last year.
“The workshop’s goal was to prioritize the challenges in HPC interconnection networks, looking toward deployment of Exascale supercomputers within the next decade; it provided a comprehensive view of the problem by [...]

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Mitrionics is offering a full day tutorial on practical FPGA acceleration for software programmers on writing Mitrion-C for the Mitrion Virtual Processor.
When: Monday, July 27, 8:00 AM - 5:00 PM
Where: SAAHPC’09, National Center for Supercomputing Applications at the University of Illinois at Urbana-Champaign
Register here
Full Story

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