by Bernard Cole, EETimes
The authors of Editor’s Top Picks for this week – Atego’s Kelvin Nilsen and Adacore’s S. Tucker Taft - believe that despite all the tools that allow embedded systems developers to maintain traditional sequential C programming techniques in the highly parallel environment of multicore design, it is now time to leave those [...]

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by Kelvin Nilsen, Atego, EETimes
Editor’s Note: In this final part in a three-part series, Atego’s Kelvin Nilsen provides guidelines on how to use the combination of the Java parallel programming language and traditional sequential C and C++ methodologies to achieve real-time multicore software operation.
When multiple processors work together to accomplish a particular work assignment, the [...]

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By Adrian Bridgwater, Dr. Dobbs
Many-core programming company Caps has added support for AMD’s GPU technology to its HMPP directive-based compiler, a product based on the OpenACC and OpenHMPP programming model. The HMPP compiler integrates a data-parallel backend for the OpenCL heterogeneous computing framework and will use the computing power of AMD GPU and APU devices.
The [...]

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by Isaac Leung, Electronics News
THE logic behind multicore technology is the ability to engage in multiple operations in parallel. With physics constraining the number of transistors that can be crammed onto microchips, manufacturers are adding on more cores in a bid to multiply performance.
While a multiple core approach has been present within the embedded sector [...]

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by Sven Brehmer, Polycore Software, (published at EETimes)
As an embedded developer who may have an application running on a single processor and would like to improve your performance or performance per watt by moving to multicore, you’d likely want to know and answer to this question: Is there a magic bullet? In other words, can [...]

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by Kelvin Nilsen, Atego, EETimes
In Part 2 in a three part series on how embedded developers can more effectively exploit the use of multicore Java, Kelvin Nilsen details the factors to consider in making a decision to shift from C and C++ to Java, as well as provides some guidelines for migrating legacy code to [...]

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by Kelvin Nilsen, Atego, EETimes
In this first part in a three part series on the use of the Java parallel programming language as the main method of doing multicore software development or or as an adjunct to traditional sequential C and C++ methodologies, Atego’s Kelvin Nilsen surveys some of the special issues that must be [...]

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by Melissae Fellet, ArsTechnica
By pre-organizing atoms in a bit of phase-change memory, information can be written in less than one nanosecond, the fastest for such memory. With write speeds comparable to the memory that powers our computers, phase change memory could one day help computers boot up instantly.
Phase-change memory stores information based [...]

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by Michael Feldman, HPCWire
ntel’s first Many Integrated Core (MIC) microprocessor is now just months away from its commercial debut. On Monday at the International Supercomputing Conference (ISC’12) in Hamburg, Intel announced that Knights Corner, the company’s first manycore product, would be in production before the end of 2012. The company also released a few more [...]

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by Linda Vu, Lawrence Berkeley National Lab
[This article refers to work done by Suren Byna, the owner of this website]
Modern research tools like supercomputers, particle colliders, and telescopes are generating so much data, so quickly, many scientists fear that soon they will not be able to keep up with the deluge. “These instruments are capable [...]

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The US Department of Energy (DOE) will be the most likely recipient of the initial crop exascale supercomputers in the country. That would certainly come as no surprise, since according the latest TOP500 rankings, the top three US machines all live at DOE labs - Sequoia at Lawrence Livermore, Mira at Argonne, and Jaguar [...]

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by Christian Simmendinger, T-Systems Solutions for Research and Daniel Grünewald, Fraunhofer ITWM, CC-HPC, published by HPCWire
As the supercomputing faithful prepare for exascale computing, there is a great deal of talk about moving beyond the two-decades-old MPI programming model . The HPC programmers of tomorrow are going to have to write codes that are able to [...]

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By Agam Shah, IDG News
Hewlett-Packard on Tuesday took the wraps off a new, low-power server platform called “Gemini,” the first implementation of which will use an upcoming Intel Atom processor code-named Centerton.
Gemini servers will be targeted at workloads that don’t need the muscle of a traditional server CPU such as an Intel Xeon and [...]

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By Timothy Prickett Morgan, The Register
For the second time in the past two years, a new supercomputer has taken the top ranking in the Top 500 list of supercomputers – and it does not use a hybrid CPU-GPU architecture. But the question everyone will be asking at the International Super Computing conference in Hamburg, Germany [...]

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For the first time since November 2009, a United States supercomputer sits atop the TOP500 list of the world’s top supercomputers. Named Sequoia, the IBM BlueGene/Q system installed at the Department of Energy’s Lawrence Livermore National Laboratory achieved an impressive 16.32 petaflop/s on the Linpack benchmark using 1,572,864 cores.
Sequoia is also one of the most [...]

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Mindspeed Technologies, Inc has introduced the Comcerto 2000 family of multi-core ARM Cortex-A CPU-based communications processors. These processor can be used in designing products for switching, routing, security, multi-service gateways, enterprise class wireless access points and controllers, network attached storage and voice-over-IP (VoIP) applications for residential, enterprise and networking equipment for small and medium businesses. [...]

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By Stacey Higginbotham, Posted on Gigaom
AMD, ARM, Texas Instruments and two smaller chip firms have teamed up to create a nonprofit that will try to unseat Intel’s x86 dominance in computing. They have formed the Heterogeneous Systems Architecture Foundation, which will standardize a single architecture for low-power computing as well as simplify the parallel-programming model [...]

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July 9–13, 2012
Siebel Center for Computer Science
University of Illinois at Urbana-Champaign
Register Here
The 2012 I2PC Summer School offers experienced programmers an opportunity to learn about multicore programming and gain mastery of cutting-edge parallel programming tools.
Program
Our program will provide a solid foundation in the fundamentals of multicore programming in Java, offer hands-on experience with the use of [...]

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by Faheem Sheikh, Mentor Graphics (published on EETimes)
It’s a common refrain heard among embedded software design teams everywhere, when the team manager declares, “We need better system power management from both the hardware and software, but we also need to optimize the design for increased functionality and performance.”
So, how can a software designer hope to [...]

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by InnovationNewsDaily Staff
Supercomputers allow the U.S. to virtually test nuclear weapons without plunging back into the Cold War — but undetected computing errors can corrupt or even crash such simulations involving 100,000 networked machines. The problem energized researchers to make an automated system for catching computer glitches before they spiral out of control.

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