By Anthony Shvets, CPU World
In August we reported about upcoming price drops of Intel microprocessors in September and October 2011. In accordance with the story, Intel reduced prices of energy-efficient Core i5 and i7 CPUs in September. The second round of price cuts happened today. The latest Intel pricelist shows 13% - 15% lower prices [...]

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by Sylvie Barak
Intel Corp.’s 22-nm Ivy Bridge CPUs will likely launch in March, one quarter later than originally planned, but well within Intel’s revised timeframe of “Spring 2012.”
Intel originally targeted late 2011 for Ivy Bridge, in time for launch at the annual Consumer Electronics Show in Las Vegas, but that timeframe had been pushed [...]

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By Lucas Mearian, ComputerWorld
OCZ yesterday released the industry’s first 2.5-in solid-state drive (SSD) with up to 1TB of capacity. The drive, based on the new Indilinx Everest controller, includes an “instant on” feature, that reduces boot times over previous OCZ SSDs by 50%.
The new Octane SSD also is priced from $1.10 to $1.30 per gigabyte, [...]

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By Arnon Peleg, Intel
Intel recently released an updated version of the Intel® OpenCL SDK for the CPU with significant new features and new performance improvements.
Available for free download at www.intel.com/go/opencl, the Intel® OpenCL SDK 1.5 makes it easy for you to design, build, debug, and profile OpenCL™ applications running on the CPU device, and is [...]

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By Asaf Shelly
This is not to say that compilers can automatically parallelize code. I would however really like to see that happen and here is an interesting and reliable way to parallelize operations. If a compiler can use this method of thinking then it can also be used as hints for developers writing code today.
C [...]

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by Joseph Yiu, ARM Ltd., EETimes
Some application developers might need to port applications from 8-bit or 16-bit microcontrollers to the Cortex-M0. By moving from these architectures to the Cortex-M0, often you can get better code density, higher performance, and lower power consumption.
Common Modifications: When porting applications from these microcontrollers to the Cortex-M0, the modifications of [...]

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by Peter Clarke, EETimes
Processor IP licensor ARM Holdings plc has revealed a power efficient Cortex-A7 processor core that it says is intended to be used alongside its top-of-the-range Cortex-A15 as part of a heterogeneous power-driven multicore strategy.
The A7 is a dual-issue, eight-stage pipeline core that has been heavily optimized for power efficiency, but supports the [...]

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by Anand Lal Shimpi, AnandTech
How do you keep increasing performance in a power constrained environment like a smartphone without decreasing battery life? You can design more efficient microarchitectures, but at some point you’ll run out of steam there. You can transition to newer, more power efficient process technologies but even then progress is very difficult [...]

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Magma Design Automation Inc., a provider of chip design software, today announced that Diodes Incorporated (Nasdaq: DIOD), a leading global manufacturer and supplier of high-quality application specific standard products within the broad discrete, logic and analog semiconductor markets, has used FineSim™ SPICE multi-CPU circuit simulation technology to tape out two highly integrated synchronous switching voltage [...]

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This week, with one day difference, new MPI versions of Open MPI and MVAPICH were announced. On Thursday, the Open MPI team announced the release of Open MPI version 1.4.4. This release is mainly a bug fix release over the previous v1.4.3 release. The team strongly recommends that all users upgrade to version 1.4.4 if [...]

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Morgan Kaufmann made available a new version of GPU Computing Gems Jade Edition. According to the web site:
This is the second volume of Morgan Kaufmann’s GPU Computing Gems, offering an all-new set of insights, ideas, and practical “;hands-on”; skills from researchers and developers worldwide. Each chapter gives you a window into the work being performed [...]

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By Nadav Rotem
Benefits of using the implicit CPU vectorization module?
SIMD instructions expose a high-level of parallelism and are used to accelerate the performance of data-parallel applications in multiple domains. The 2nd Generation Intel® Core Processor Family codenamed “Sandy Bridge”, features the Intel® AVX instruction set, which has 8 wide floating point SIMD processing. Applications which [...]

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At Fusion 2011, AMD demonstrated its next generation graphics processor, based on the cutting-edge 28 nm process technology. The demonstration was delivered by Corporate Vice President and General Manager of AMD’s Graphics Division, Matt Skynner, as part of his keynote titled, “Enabling the Best Visual Experience.” Skynner demonstrated a notebook-based version of AMD’s 28 [...]

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by Stacey Higginbotham
Memory chip giants Samsung and Micron have joined forces to create a new type of memory chip designed for high performance computing in a world with much faster broadband networks. The two firms said Thursday that they have formed the Hybrid Memory Cube Consortium to build a chip that can send information from [...]

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by Dean Takahashi
The Oak Ridge National Laboratory plans to create what could become the world’s most powerful supercomputer, Titan, based on a Cray supercomputer with 18,000 microprocessors from Advanced Micro Devices and an equal number of Nvidia graphics chips.

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Book Title: Heterogeneous Computing with OpenCL
Authors: Benedict Gaster, David R. Kaeli, Lee Howes, Perhaad Mistry, Dana Schaa
Heterogeneous Computing with OpenCL teaches OpenCL and parallel programming for complex systems that may include a variety of device architectures: multi-core CPUs, GPUs, and fully-integrated Accelerated Processing Units (APUs) such as AMD Fusion technology. Designed to work on multiple [...]

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In May, chip startup Adapteva debuted Epiphany, a manycore architecture designed to maximize floating point horsepower with the lowest possible energy footprint. The initial silicon was a 16-core processor, implemented on the 65nm process node. This week, the company announced it has taped out a 64-core version of the design on the 28nm process node, [...]

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TVS announces the Multicore Challenge for 2012. The Multicore Challenge is an annual event that considers the challenges surrounding developing software products built on multicore hardware. Held physically in Bristol but webcast around the world, the meetings provide a chance to listen to the latest multicore technology. Designers, engineers and managers may sign up to [...]

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TACC announced today plans to deploy one of the world fastest supercomputer – a 10 petaflop machine in the beginning of 2013. The money is coming from the National Science Foundation\’s (NSF) “eXtreme Digital” (XD) program.
When completed, the system will comprise several thousand Dell servers with Intel Sandy Bridge-EP CPUs (PCI-Express Generation 3). The [...]

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