by Anand Lal Shimpi, AnandTech
During the final keynote of IDF, Intel’s Justin Rattner demonstrated a new stacked DRAM technology called the Hybrid Memory Cube (HMC). The need is clear: if CPU performance is to continue to scale, there can’t be any bottlenecks preventing that scaling from happening. Memory bandwidth has always been a bottleneck we’ve been worried about as an industry. Ten years ago the worry was that parallel DRAM interfaces wouldn’t be able to cut it. Thankfully through tons of innovation we’re able to put down 128-bit wide DRAM paths on mainstream motherboards and use some very high speed memories attached to it. What many thought couldn’t be done became commonplace and affordable. The question is where do we go from there? DRAM frequencies won’t scale forever and continually widening buses isn’t exactly feasible.

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