by Timothy Prickett Morgan, IT Jungle
In the latest roadmap, IBM is showing that the Power7+ chip will use a 32 nanometer process, down significantly from the 45 nanometer process used with the Power7 chips that first came to market in February 2010 and were rolled up and down the Power Systems line through August of last year. The updated roadmap says that the Power7+ chips will run faster, and will include a “very large cache” and “accelerators.” Of course, the Power7 chips already have a 32 MB on-chip L3 cache implemented in embedded DRAM.

My guess is the shrink to 32 nanometer will allow IBM to crank the clocks on the processors by somewhere between 25 and 30 percent. IBM could boost the eDRAM cache size, but that may require a lot of redesign work, and the whole point of the “evolution” part of the cycle is to not mess with the design too much. It is almost certain that IBM will stick with four, six, and eight core variants with the Power7+ chips.

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