by Steve Gunther, Anant Deval, Rajesh Kumar, and Edward (Ted) Burton, Intel Corporation
Abstract: Maximizing energy efficiency was a key goal on the design of the The Intel® microarchitecture code name Nehalem, which was conceived as a modular architecture with multiple cores that would scale from very small mobile platforms to very high-performance, server configurations. Building a scalable product while working within the voltage and leakage scaling physics required several innovative technologies including power gate transistors, dramatically improved Intel Turbo Boost Technology, and Dynamic Voltage Positioning. Power-plane partitioning, clocking strategies and cache, and memory and I/O power-management algorithms were all tuned to maximize energy efficiency while providing breakthrough product performance across a wide range of workloads. The resulting algorithmic complexity drove the inclusion of an embedded micro-controller (the Power Control Unit, or PCU) to implement the power-management decisions and control. In this article we describe the key power-management features implemented on the 45nm and 32nm Nehalem family of products.
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