By Timothy Prickett Morgan
Fast and reliable non-volatile memory of some sort that will replace flash memory is the dream of more than a few semiconductor researchers and chip makers. And boffins at IBM Research in Zurich, Switzerland, think they have come up with a new encoding technique that will allow for multi-level cell (MLC) phase [...]

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By Lucas Mearian
IBM Thursday announced a breakthrough in computer memory technology, which may lead to the development of solid-state chips that can store as much data as NAND flash technology but with 100 times the performance and vastly greater lifespan.
Currently, NAND flash memory products, such as SSDs, have write rates as high as 2Gbit/sec.

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by Arnon Peleg
Following the successful alpha and beta releases on software.intel.com, which received very positive feedback, Intel is releasing today the gold version of the Intel® OpenCLSDK 1.1 for the CPU on www.intel.com/go/opencl. This SDK is conformant with the OpenCL™ 1.1 specification.
Along with this release, here are new and updated tips and tutorials to ease [...]

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by Cody Croxton, Ben Eckermann and David Lapp
Multicore processing has enabled higher and higher levels of processing capability, but with a price: higher levels of power consumption. Cascading power management is a technique that steers tasks to a smaller number of cores during non-peak activity periods so that the idle cores can enter a minimal-power [...]

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Werner Obermaier – Head of Product Marketing at Vincotech GmbH
The increasing request for motor drives with higher power levels is also driving the demand for power modules providing higher currents. The conventional approach to fulfill this requirement is to look for dedicated high current power modules. This article describes the alternative approach of paralleling IGBTs [...]

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ispc is a new compiler for “single program, multiple data” (SPMD) programs. Under the SPMD model, the programmer writes a program that mostly appears to be a regular serial program, though the execution model is actually that a number of program instances execute in parallel on the hardware. ispc compiles a C-based SPMD programming language [...]

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By Mark Overton
For optimal performance, subcycle RNGs can be shaped many different ways according to application need and processor capabilities
In the first part of this two-part series, Fast, High-Quality, Parallel Random Number Generators , Mark Overton described a new family of fast random number generators based on the subcycles that can be implemented using simple [...]

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By Shameem Akhter and Jason Roberts
Too many threads running, too many held locks, and too many threads waiting on a lock are problems that can be solved with a little know-how
Parallel programming has been around for decades, though before the advent of multicore processors, it was more of an esoteric discipline. Now, numerous programmers have [...]

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Aater Suleman discusses Gustafson’s law for parallel computing.
Lemma 1:
There exists workloads that are gaseous in nature: When provided with more compute power, they expand to consume the newly provided power.
Such programs are more common than you think.

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by Aater Suleman, Future Chips
Who should avoid using the term “Amdahl’s law”?
As with any analytic model, Amdahl’s law should only be used when a workload fits the programming model assumed by the model. There are many programs that do not fit this model. Fundamentally, Amdahl’s law assumes that any code which cannot be parallelized is [...]

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by Lauren Sommer
As supercomputers grow, so does their energy appetite. Researchers are trying to solve that problem by using a smaller, more pervasive technology.
Supercomputers have improved at a break-neck speed, especially if you look back to the Cray-1. In 1976, this six-foot tall tower of wires was the most powerful supercomputer the world had ever [...]

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by Mike Mayberry, Vice President, Technology & Manufacturing Group, and Director, Components Research
In the last blog, I talked about optimizing materials to get higher mobility and optimizing the structure to get to better coupling. Still a third optimization direction is to look at different types of device operation, particularly as we try to make very [...]

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By Noah Clemons
In the last blog, I gave a crash course on how to create an Intel® parallel_for with lambda expressions, which is another way of letting the compiler do the tedious work of creating a function object. I’d like to give a few high-level descriptions of some Generic Parallel Algorithms included in Intel® [...]

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This white paper is second in series of white papers on OpenCL describing status of OpenCL implementation and available tools for developers using Intel OpenCL SDK.
The Intel OpenCL 1.1 specification Beta implementation for CPU (Core 2 Duo (Penryn) or later CPUs) can be retrieved from http://software.intel.com/en-us/articles/opencl-sdk. It is still evolving into a mature product so [...]

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by Wayne Wolf
Embedded system designs must meet several different design criteria. The traditional operations research approach of defining a single objective function and perhaps some minor objective functions, along with design constraints, may not adequately describe the system requirements.

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by Douglas Eadline for Cluster Monkey
The remarkable computation power of General Purpose Graphical Processing Units (GP-GPUs) has led them to steadily gain traction in High Performance Computing (HPC). But creating GP-GPU programs can require new programming methods that often introduce additional work and code revisions, or even re-writes, and frequently become an obstacle to the [...]

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by Shameem Akhter, Jason Roberts, and Andrew Binstock
For multithreaded software to run optimally, developers must understand subtle aspects of memory access
Parallel programming is gaining favor as the multicore architecture becomes ubiquitous. On processors based on the x86 architecture, running threads in parallel presents memory problems beyond the typical concerns of keeping threads from interfering with [...]

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by Peter Clarke, EETimes
Fabless many-core processor vendor Tilera Corp. has launched its Tile-Gx 3000 family of 40-nm processors claiming they provide a 10-fold improvement over Intel’s SandyBridge processor in terms of performance-per-watt.

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by Kathleen Mitchell
Steven Frank, Jef Sharp, Jeff Hausthor, and Stephan Rogers are heading up a team whose work is so revolutionary that customers who hear about it say it is almost too good to be true.
“The feedback we are getting shows that what we are doing is the Holy Grail,” said Frank, CEO of Panève [...]

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Worldwide server shipments grew 23 percent year over year in the first quarter of 2010, while revenue increased 6 percent, according to Gartner, Inc.
“We’ve seen a return to growth on a worldwide level, but the market has not yet returned to the historical quarterly highs that were posted in 2008, and there were some interesting [...]

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