by Jan A. Zverina, San Diego Supercomputer Center
The news late last year that China’s GPU-rich Tianhe-1A supercomputer was ranked the fastest system in the world focused attention – and a lot of discussion – within the HPC community about the advantages of graphics processing units (GPUs) versus central processing units (CPUs) used in many systems.
While [...]

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Uploaded by RichReport, InsideHPC
In this video, Jack Dongarra from the University of Tennessee presents Architecture-Aware Algorithms and Software for Peta & Exascale Computing. Recorded at the National HPCC Conference in Newport: http://www.hpcc-usa.org.

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by Michael Cooney, NetworkWorld
Microsoft researchers are experimenting with a programmable, low-cost prototype switch they say could help support cloud or other network-delivered services.
Called ServerSwitch, the package integrates a high performance, programmable ASIC switching chip with a fully programmable multicore commodity server and control software designed to handle data center network traffic more efficiently than [...]

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It seemed that long forum debates about methods of measuring algorithms running time, functions to use and precision that should be expected were over. Unfortunately, we have to return to this question once again. Today we will discuss the question how we should measure speed of a parallel algorithm.
I want to say right away that [...]

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Presenter: Xing Zhou, Department of Computer Science, Illinois
When: Thursday, March 31, 2011 at 2 PM (Central Time)
Live Stream: http://media.cs.illinois.edu/live/UPCRClive.asx
Live Chat: http://www.upcrc.illinois.edu/chat/
Abstract
Heterogeneous Systems have the potential to provide cost and power efficient performance for parallel programs. In order to achieve good performance, programmers must manually optimize for locality and parallelism taking into account the characteristics [...]

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by Agam Shah
The Multicore Association is establishing specifications for a programming model that will reduce the complexity involved in writing software for multicore chips used in smartphones, tablets, and other embedded systems.
The association is putting together a cohesive set of foundation APIs (application programming interfaces) to standardize communication, resource sharing, and virtualization spanning cores on [...]

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by Michael Wolfe, Compiler Engineer, The Portland Group, Inc.
As we move towards exascale, we want to take advantage of all of these. We need to expose parallelism at all the levels, either explicitly in the program, or implicitly within the compiler. We need to express this parallelism, in a language and in the generated [...]

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by George Leopold
As Moore’s Law runs out of steam and computing goes mobile, technologists are searching for ways to make the leap to new parallel programming frameworks that can leverage low-power multicore architectures. The move has been spurred by growing industry concern that today’s microprocessor computing engines have hit a “power wall”. That in turn [...]

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By Dan Olds, Gabriel Consulting
2010 was the breakout year for Nvidia’s Tesla division, according to Tesla VP Andy Keane, who spoke at the company’s Industry Analyst Day earlier this month. I think it’s pretty obvious that he’s right, and a quick review of the last year tells the story.
Three of the top five systems on [...]

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The advances in mobile computing and the decline of Moore’s Law adds to growing industry concern that today’s microprocessor computing engines have hit a “power wall,” calling for chip designers and software developers to find ways to shift to new parallel programming frameworks that can harness low-power multi-core architectures.

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Pebble Bay will discuss the successful development of BSPs, drivers and other software for these multicore architectures at “Multicore Processors - Embedded Software Network” on Tuesday 5th April at ARM near Cambridge.

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July 25-29, 2011
Siebel Center for Computer Science
University of Illinois at Urbana-Champaign
The 2011 UPCRC Illinois Summer School offers experienced programmers, with little or no exposure to parallelism, an opportunity to learn about multicore programming.

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by Douglas Eadline Ph.D.
When multi-core processors first appeared, I wanted to know the answer to a simple question. If a program runs on a single core in X number of seconds, then Y copies should run in the same amount of time, provided Y is less than or equal to the number of cores and [...]

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by Rick Merritt
Hoping to get a jump on archrival ARM Ltd., MIPS Technologies aims to launch this fall at least two 64-bit synthesizable cores. Unlike its now-discontinued offerings from several years ago, the Prodigy family will include members that support multithreading and issue multiple instructions per clock cycle.

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by Richard Gerber, Aart J.C. Bik, Kevin B. Smith, and Xinmin Tian
Branch mis-predictions can cause an enormous amount of inefficiency and be very costly in terms of the run time of a function. Improving branch predictions involves two steps: identifying where mis-predictions are occurring and at what ratio to correct predictions, and optimizing the [...]

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by Tom Simonite
Silicon may underpin the computers that surround us, but the rigid inflexibility of the semiconductor means it cannot reach everywhere. The first computer processor and memory chips made out of plastic semiconductors suggest that, someday, nowhere will be out of bounds for computer power.

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by Rajive Joshi, Ph.D.
As businesses struggle to handle large volumes of data rapidly, technologies used in industry and by the masters of the universe on Wall Street are suddenly becoming fashionable…again
Wired and wireless communication networks are making data collection and transmission cheap and widespread. In the future, networks will weave many devices and subsystems into [...]

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by Nicole Hemsoth
While the advent of multicore systems has opened doors for unprecedented cost and power reductions for scalable HPC, it has been clear for some time that this creates a series of issues that will need to be addressed in coming years, particularly for programmers.

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This article originally posted on August 24, 2009. Since then, OpenCL gained a lot of popularity and a number of tutorials and sample codes have been developed. In this article, we update the original article with recent resources and removing any dead links.
We provided many resources on parallel programming tutorials. The following are the ones [...]

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by Richard Gerber, Aart J.C. Bik, Kevin B. Smith, and Xinmin Tian, Intel Corporation
Parallelization using threads on multiple logical processors is an attractive and effective way to optimize software. As technologies to simulate multiple processors (such as Intel’s Hyper Threading technology) and processors containing multiple cores become the standard for even consumer level computing, the [...]

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