by Dylan McGrath
Intel Corp. disclosed more technical details of its 32-nm Sandy Bridge processor at the International Solid-State Circuits Conference here Tuesday (Feb. 22), including further description of its modular ring interconnect, design techniques used to minimize the cache’s operational voltage and the inclusion of debug bus for monitoring traffic on the interconnect.

The 32-nm Sandy Bridge processor integrates up to four x86 cores, a power/performance optimized graphic processing unit (GPU) and DDR3 memory and PCI Express controllers on the same die, according to the paper presented at ISSCC Tuesday by Ernest Knoll, a designer at Intel’s design center in Haifa, Israel. Sandy Bridge features 1.16 billion transistors and a die size of 216 square millimeters, Knoll said.

The Sandy Bridge IA core implements several improvements that boost performance without increasing power consumption, including an improved branch prediction algorithm, a micro-operation cache and a floating point advanced vector extension, according to the paper. Also, the devices’ CPUs and GPU share the same 8MB level-3 cache memory, according to the paper.

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