by Steve Conway [Published in Aug 2010]
Big challenges lie on the software side in efficiently corralling hardware’s runaway parallelism

At an IDC HPC User Forum meeting in 2005, Paul Muzio, director of the HPC Center at City University of New York, said that an application engineer’s ideal petascale supercomputer would have one powerful processor with direct access to main memory. By contrast, a computer scientist’s ideal petascale system would have hundreds of thousands of processors of different types and an innovative, distributed memory architecture.

“Unfortunately for many users,” he added, “the computer scientist’s system may be the one that’s built in the near future, as the technology to do otherwise does not exist. The challenge will be to build this kind of system but make it look like the kind the applications the software engineer wants.”

Fast forward five years to today, and Paul Muzio’s expectation is manifest. The first petascale supercomputers — now deployed in the U.S., Germany and China — employ more than 100,000 processor cores each, multiple processor types in most cases, and distributed memory architectures.

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