By Mary Jo Foley
Today, Microsoft’s programming model for the cloud is .Net. At some point in the future, it may become Orleans.
Orleans is a Microsoft Research project. At Microsoft’s Professional Developers Conference in Redmond this week, the company is showing off Orleans as one of its research demos.
Orleans is currently a project in Microsoft’s eXtreme [...]

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By Tommy Minyard and Dan Stanzione, Texas Advanced Computing Center
Intel has continued to increase core count with the introduction of the Westmere processor, and upcoming processors will feature both more bandwidth and more cores (as will processors in competing lines). These changes will mean an overall improvement, of course, but also will require some deeper [...]

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by Michael Feldman, Editor, HPCWire
As we move from multicore to manycore processors, memory bandwidth is going to become an increasingly annoying problem. For some HPC applications it already is. As pointed at in a recent HPCwire blog, a Sandia study found that certain classes of data-intensive applications actually run slower once you try [...]

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By Timothy Prickett Morgan
With the supercomputing community in the Western economies freaking out just a little bit that China has come out of nowhere to take the lead in supercomputing, and the US supposedly getting ready to allocate $5bn in an effort to push up into the exacale realm, IDC could not find a [...]

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by Rich Brueckner, insideHPC
The National Supercomputing Center in Tianjin, China announced that their new Tianhe-1A supercomputer has set a new performance record of 2.507 petaflops on the LINPACK benchmark, making it the fastest system in the world. While these results have been submitted to TOP500.org, their semi-annual list of the world’s fastest systems will not [...]

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by David Kalinsky, Kalinsky Associates
Users of real-time operating systems (RTOS) are familiar with the various kinds of semaphores they offer. Depending on which RTOS you choose, these may include counting semaphores, binary semaphores and mutex semaphores.
As the embedded software world transitions into the era of multi-core processing, these 3 “traditional” kinds of [...]

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By RAVI (Intel)
Multi-core processors are ubiquitous now and it has become necessary to exploit the additional processing capabilities afforded by the multiple cores. Software written for single-core processors with serial execution in mind now needs to be retargeted to multi-core processors. We are obviously talking about programs which execute on a single machine and in [...]

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by John Fruehe
One of the most interesting features planned for our next generation core architecture, which features the new “Bulldozer” core, is something called the “Flex FP”, which delivers tremendous floating point capabilities for technical and financial applications.
For those of you not familiar with floating point math, this is the high level stuff, not [...]

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CAPS, global leader in manycore programming tools and services today announced that its HMPP compiler now supports Microsoft Windows HPC Server 2008 R2 and Visual Studio 2008.
Based on GPU programming and tuning directives, HMPP offers an incremental programming model that allows developers with different levels of expertise to fully exploit GPU hardware accelerators in their [...]

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by Tiffany Trader, Associate editor of HPCwire
Moore’s Law is dead, or is it? There’s the camp that believes Moore’s Law, which states that transistor density on integrated circuits doubles about every two years, will be viable for only another decade or two. But there’s another camp that thinks the technology already exists to extend [...]

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by P.J. Tanzillo
High performance computing isn’t about technology at all. Rather, it’s all about the answers to difficult questions. The technology is simply a means to an end, and novel advances in technology are pioneered by scientists only when there is no other way to get to an answer in an acceptable time.
In the [...]

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By Ed Sperling
The move toward concurrent design is escalating at advanced nodes, driven more by the need to ensure that everything works than previous efforts aimed at efficiency and time-to-market.
While the concept has surfaced before in limited doses—engineers and EDA companies have been talking about doing things more things simultaneously for the better part of [...]

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by Marco Chiappetta and Dave Altavilla
While attending a press event out in Los Angeles, California last week, to discuss the impending Radeon HD 6870 and HD 6850 launch, we had the chance to get an early look at some of the first, fully functional samples of AMD’s upcoming “Llano” processor, or APU (Applications Processer Unit).
For [...]

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By Elizabeth S
The “Introducing Intel® Parallel Building Blocks” Technical Presentations were held on Thursday, September 23, 2010. If you missed this technical presentation you can view the recording which is available for download.
Full Story

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By Elizabeth S
The “Adding Parallelism with Intel® Parallel Advisor 2011: No Parallelism Experience Required” Technical Presentations were held on Tuesday, October 12, 2010. If you missed this technical presentation you can view the recording which is available for download.
Full Story

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by Caroline Connor, for HPCwire
John Gustafson is known for his work in HPC, describing the notion of weak scaling (Gustafson’s Law), introducing the first commercial computer cluster, winning the first Gordon Bell Award and all that.
HPCwire: John, you’re known for your “Reevaluating Amdahl’s Law” paper. Have you ever met Gene Amdahl? Is there [...]

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Making computers faster means relying on the central processing unit (CPU) less than ever before.
The Central Processing Unit (CPU)–the component that has defined the performance of your computer for many years–has hit a wall.
In fact, the next-generation of CPUs, including Intel’s forthcoming Sandy Bridge processor, have to contend with multiple walls–a memory bottleneck (the bandwidth [...]

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by Douglas Eadline, Ph.D.
If you have read any of my past columns, you will notice I like to test assumptions and try obvious things. I often find that things do not always work the way people expect. As more and more cores show up in processors, one of the burning questions I have is; “How [...]

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by Douglas Eadline, Ph.D. (published in Dec 2007
No matter how you cut it, coding for multicore is really just parallel programming. Once you’ve realized that, it’s time to look at the options, whether your existing codebase will scale, or if you need to rewrite your code and how.
As stated in The Multicore Programming Challenge, parallel [...]

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The fast, random access memory used to service modern multicore processors performs well, but when the power is switched off, the digital information stored therein is lost. Yet the ability to retain information without power is critical to the function of virtually any electronics device. That makes non-volatile (NV) memory an essential ingredient for a [...]

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