By John Blyler
Power Architecture member IBM talks about scalability, multicore, multithreading, and software challenges in today’s electronics market.
Designing electronic systems has never been easy. Processors—the critical component of any electronics—continue to grow in complexity. The move toward multicore extends those inherent design complexities to the hardware-interconnect and software-development domains.
Two main processor architectures have dominated the [...]

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By AB Periasamy
Now that hypervisors are mature management tools, monitoring capabilities and standards are evolving. Resources in the cloud are more dynamic, multi-tenant and large-scale. However, full data center virtualization and the cloud cannot be complete without virtualizing the storage layer. Storage virtualization demands an entirely new software-based approach.
Server virtualization technologies for Linux have advanced [...]

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by Agam Shah, IDG News
Smartphones are on the verge of becoming more powerful, with chip makers readying dual-core chips that could accelerate multimedia and application performance on handheld devices.
Most smartphones are only capable of 720p video and come with processors touching speeds of around 1GHz, but users are demanding more performance, analysts said. A new [...]

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Oracle will continue developing Sparc microprocessors but focus on chips based on a single core design at a time, probably packing 32 of them in a single chip by 2015. The move is part of an overall shift to a more streamlined road map for the former Sun Microsystems which also continues to use [...]

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eMuCo (Embedded Multi-Core Processing for Mobile Communications) is a project aimed at opening the door to the next generation of smart phones by bringing the power of multicore and virtualization to mobile phones. eMuCo started as a European initiative of universities and companies in the mobile embedded market to explore the principles, suitability, and [...]

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by Steve Conway
Big challenges lie on the software side in efficiently corralling hardware’s runaway parallelism
At an IDC HPC User Forum meeting in 2005, Paul Muzio, director of the HPC Center at City University of New York, said that an application engineer’s ideal petascale supercomputer would have one powerful processor with direct access to main [...]

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CUDA is a computing architecture designed to facilitate the development of parallel programs. In conjunction with a comprehensive software platform, the CUDA Architecture enables programmers to draw on the immense power of graphics processing units (GPUs) when building high-performance applications. GPUs, of course, have long been available for demanding graphics and game applications. CUDA now [...]

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by Eric Merritt
Over the last few weeks I have had several conversations with people about concurrency, more specifically the ways in which shared information is handled in concurrent languages. I have gotten the impression that there isn’t really a good understanding of whats out there in the world of concurrency. That being the case it [...]

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by Bartosz Milewski
Concurrent programming has been around for quite some time (almost half a century), but it was mostly accessible to the highest ranks of the programming priesthood. This changed when, in the 2000s, concurrency entered prime time, prodded by the ubiquity of multicore processors. The industry can no longer afford to pay for hand-crafted [...]

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NVIDIA-Led Team Receives $25 Million Contract From DARPA to Develop High-Performance GPU Computing Systems
A team led by NVIDIA has been awarded a research grant of $25 million by the Defense Advanced Research Projects Agency (DARPA), the U.S. Defense Department’s research and development arm, to address what the agency calls a “crisis in computing.”
The four-year [...]

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by Jason Lane
Intel and AMD have done their best to differentiate the x86 architecture as much as possible while retaining compatibility between the two CPUs, but the differences between the two are growing. One key differentiator is hyperthreading; Intel does it, AMD does not.
Multicore and HyperThreading (referred to as “HT”) are not the same, [...]

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by Michael Wolfe, Compiler Engineer, The Portland Group, Inc.
In May, Intel announced the Many Integrated Core (MIC, pronounced “Mike”) architecture, with a development kit codenamed Knights Ferry. The Knights Ferry chip was described broadly by Kirk Skaugen at his ISC’10 keynote talk in Hamburg, Germany. Slide 33 from his presentation makes the Knights Ferry [...]

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HPC Project has introduced Version 1.0 of the Par4all, an open parallelization platform that provides automatic code generation for NVIDIA GPU-based hybrid architectures.
Pa4All is an open-source environment to do source-to-source transformations on C and Fortran programs for parallelizing, optimizing, instrumenting, reverse-engineering, etc. on various targets, from multicore system-on-chip with some accelerators up high-performance computers and [...]

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CriticalBlue, a pioneer in embedded multicore software analysis, exploration and verification tools, and Cavium Networks, Inc. /quotes/comstock/15*!cavm/quotes/nls/cavm (CAVM 27.22, -0.22, -0.80%) , provider of semiconductor products that enable intelligent processing for networking, communications and the digital home, announced today immediate support for the OCTEON(R) and OCTEON II architectures within CriticalBlue’s Prism software analysis, [...]

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by Michael Vizard
One of the things that has limited statistical analysis specifically and business intelligence in general has been the cost of the software. In the last couple of years, however, academic institutions have been overcoming that particular limitation by embracing an open source language for analytic applications simply known as R.
The tradeoff [...]

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By Katherine Noyes
The latest version of the Linux kernel was released on Sunday, offering not just a host of bug fixes but also new features designed for multicore environments.
Most notably, tapping technology contributed by Google , Linux version 2.6.35 includes Receive Packet Steering (RPS) and Receive Flow Steering (RFS) features that help to spread network [...]

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By Jim Dempsey
The subject matter of this article is: How to optimally tune a well known algorithm. We will take this well known (small) algorithm, a common approach to parallelizing this algorithm, a better approach to parallelizing this algorithm, and then produce a fully cache sensitized approach to parallelizing this algorithm. The intention of this [...]

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A new approach to processing X-ray data could lower by a factor of ten or more the amount of radiation patients receive during cone beam CT scans, report researchers from the University of California, San Diego.
Cone beam CT plays an essential role in image-guided radiation therapy (IGRT), a state-of-the-art cancer treatment. IGRT uses repeated scans [...]

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by Wolfgang Gentzsch, DEISA Advisor, Open Grid Forum Director
The increasing number of CPU cores makes me worry about the relatively low utilization of the recent manycore CPUs, along with the potential increase in wasted energy, and the low degree of parallelization of many applications submitted to many-core based servers. EXludus CEO Dale Geldart [...]

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