by Steven Leibson
ISQED, the International Symposium for Quality Electronic Design, is currently underway here in San Jose at the Doubletree Hotel. I listened to three keynotes yesterday and will summarize them in three blog entries. The first keynote, by Ramanan Thiagarajah of Inphi Corp discussed the effect that the adoption of multicore CPUs is having on server design. First, we’re getting a lot more CPU performance. Using 2007 as a baseline year, Thiagarajah mapped the increase in computing horsepower over four years. In 2007, we had 4-core CPUs and dual-socket server blades or motherboards for a total of eight cores per board. By 2009, some servers were using 12-core CPUs in 2-socket boards (seems a bit premature to me, but there it is), which boosted performance by 3x relative to the year 2007. By 2011, said Thiagarajah, expect to see 32-core CPUs running in 4-socket systems with 16x the CPU performance of the baseline year. (Again, seems a stretch but they’re not my estimates.)

However, because all of the processor cores these multicore CPUs must access main memory through the chip’s memory interface, a major memory bottleneck has been building. There are more CPUs sipping from the memory pool through a straw that’s not getting any bigger. Memory and memory interfaces are not scaling in a cost-effective way, said Thiagarajah. In particular, frequency scaling with larger memory arrays is a major challenge because it becomes harder and harder to drive the loads at small lithographies. In addition to just driving the load, there are mounting signal-integrity challenges in attempting to drive larger memory arrays at high speed. And finally, getting more performance/Watt is a continuing challenge that grows with the size of the memory array and the operating frequency of the memory interface.

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