by Greg Pfister
Memory bandwidth. And, most likely, software cost. Now that I’ve given you the punch lines, here’s the rest of the story.

Larrabee, Intel’s venture into high-performance graphics (and accelerated HPC), the root of months of trash talk between Intel and Nvidia, is well-known to have been delayed sin die: The pre-announced 2010 product won’t happen, although some number will be available for software development, and no new date has been given for a product. It’s also well-known for being an architecture that’s clearly programmable with standard thinking and tools, as opposed to other GPGPUs (Nvidia, ATI/AMD), which look like something from another planet to anybody but a graphics wizard. In that context, a talk at Stanford earlier this month by Tom Forsyth, one of the Larrabee architects at Intel, is an interesting event.

Tom’s topic was The Challenges of Larrabee as a GPU, and it began with Tom carefully stating the official word on Larrabee (delay) and then interpreting it: “Essentially, the first one isn’t as cool as we hoped, and so there’s no point in trying to sell it, because no one would buy it.” Fair enough. He promised they’d get it right on the 2nd, 3rd, 4th, or whatever try. Everybody’s doing what they were doing before the announcement; they’ll just keeping on truckin’.

But, among many other interesting things, he also said the target memory bandwidth – presumably required for adequate performance on the software renderer being written (and rewritten, and rewritten…) was to be able to read 2 bytes / thread / cycle.

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