by Greg Pfister
Memory bandwidth. And, most likely, software cost. Now that I’ve given you the punch lines, here’s the rest of the story.
Larrabee, Intel’s venture into high-performance graphics (and accelerated HPC), the root of months of trash talk between Intel and Nvidia, is well-known to have been delayed sin die: The pre-announced 2010 product won’t [...]

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by Jim Dempsey
In the previous post we looked at using the QuickThread toolkit to write a two-stage input pipeline to boost the performance of the input side of your application. Today we look at using the QuickThread toolkit to write a high-performance output end of an application. QuickThread is available from QuickThread Programming.
Recap summary from [...]

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The first textbook of its kind, Programming Massively Parallel Processors: A Hands-on Approach launches today, authored by Dr. David B. Kirk, NVIDIA Fellow and former chief scientist, and Dr. Wen-mei Hwu, who serves at the University of Illinois at Urbana-Champaign as Chair of Electrical and Computer Engineering in the Coordinated Science Laboratory, co-director of the [...]

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There was a post on comp.programming.threads this morning asking for a definition of these terms. To write good multithreaded code you really need to understand what these mean, and how they affect the behaviour and performance of algorithms with these properties. Here are some definitions provided by Anthony Williams.
Blocking
A function is said to be blocking [...]

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by Aharon Etengoff, TG Daily
“Saint Steven Jobs has finally come down from the mountain top bearing Apple’s “magical and revolutionary” tablet device. The iPad - which weighs just 1.5 pounds - is powered by Apple’s next- generation A4 system-on-a-chip and offers a relatively long battery life of up to 10 hours.
In addition, the iPad [...]

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by Anand Lal Shimpi
In 2008 Intel introduced the Diamondville platform. This was the Atom platform that was used in the vast majority of netbooks and nettops. You had an Atom processor (codename: Diamondville) and Intel’s 945GSE chipset. The memory controller was located on the chipset which was built on a 90nm process that ended up [...]

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Oracle’s plans for Java and the proposed Sun Cloud public computing platform became clearer Wednesday, with Oracle executives giving another big thumbs-up to Java but a thumbs-down to Sun Cloud.
Under Oracle’s new stewardship, Java will be expanded to more application types while the public process for amending Java will be made more participatory, an Oracle [...]

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by Kim Hartman and Paul Fischer
PC-compatible industrial computers are increasing in computing power at a rapid rate due to the availability of multi-core microprocessor chips, and Microsoft Windows has become the de-facto software platform for implementing human-machine interfaces (HMIs).
PCs are also becoming more reliable. With these trends, the practice of building robotic systems as complex [...]

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By Vincent Perrier
Specifying and validating embedded systems and chips becomes increasingly challenging as feature sets and non-functional constraints grow. It’s especially difficult when the system involves a multicore programmable platform, which includes several processing engines such as microprocessors, microcontrollers or DSPs, that run application software distributed across the various cores.
The development of the hardware (HW) [...]

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The Linux kernel is monolithic: it means that every hardware driver runs in kernel memory space. Every time you add a driver, you add stuff to the kernel. Moreover, for performance reasons, several user-space elements make their way into the kernel and increase its bloat even further.
Moreover, Linux has historically been developed for x86 platforms, [...]

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By Ron Wilson, Executive Editor — EDN
The dual pressures of higher data bandwidth and media data types are changing networks from endpoint to core. And wireless networks, forced to shift from their rapid deployment of HSPA to LTE while simultaneously staggering under the blows of growing smart-phone use, are taking the brunt of the changes. [...]

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Time is no longer a best performance programming tool, by just waiting 18 months for a doubling of performance. The discussion initiated by last year’s panel led to the conclusion that parallelism must seamlessly be woven throughout the CS curriculum. This year provides a diabolic panel focused on details; the six panelists will spend 5 [...]

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By Jon Bullinger
Review the archived webinar about using Intel Concurrent Collections for C++ to take advantage of multi-core without worrying about low level threading constructs or thread scheduling. Includes practical examples. Also see the accompanying white paper.
Full Story
White Paper

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Having lost the CPU performance race, AMD has been focusing on the low and mid-range PC market instead. Today the thorn in Intel’s side is expanding its Phenom II and Athlon II lineup with some minor speed increases. The new Athlon II X2, X3, X4 and Phenom II X2/X4 (energy efficient) families have new siblings [...]

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by Gaston Hillar
Sometimes, parallelized code can run slower than its sequential version because Intel Turbo Boost Technology can make the latter run at faster clock frequencies than the former. Therefore, if you work with a microprocessor with Intel Turbo Boost Technology enabled, you will have to pay attention to the changes introduced by this technology.
The [...]

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by Jim Dempsey
Welcome to the Quick Threads blog. Today we will look at using the QuickThread threading toolkit to write a two-stage input pipeline to boost the performance of the input side of your applications. QuickThread is available from QuickThread Programming, LLC http://www.quickthreadprogramming.com.
As an example program, we will use the Black-Scholes benchmark included in the [...]

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Mindspeed Technologies (News - Alert), Inc. (NASDAQ: MSPD), a leading supplier of semiconductor solutions for network infrastructure applications, today announced the first in a family of highly integrated and cost-effective application-specific SoC solutions targeting the low-power requirements and heavy processing demands of an unprecedented variety of emerging next-generation mobile broadband basestation platforms, from enterprise femtocells [...]

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Europe’s contribution to high performance computing will be one of the highlights at this year’s International Solid State Circuits Conference (ISSCC), the leading event of its kind.
Engineers from IBM’s Boeblingen facility in Germany will be providing more details on the company’s POWER7 processor, which is aimed at high end servers. The highly parallel and scalable [...]

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The 16th International Symposium on High-Performance Computer Architecture (HPCA) and 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010) were held in Bangalore, India between January 9th and 14th. These are two premier conferences covering research in a wide range of topics in high-performance computer architecture and parallel programming.
There [...]

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The U.S. Department of Energy (DoE) has awarded Columbia University $2.8 million in Recovery Act economic stimulus funding to design power converters that efficiently regulate voltage for multi-core processors right on the chip, which could save U.S. data centers billions of kilowatts of energy yearly.
IBM Research and Cornell University will also participate in the program [...]

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