by Mark LaPedus
The latest craze in next-generation chip design is 3-D. IC makers are exploring the possibly of stacking current devices in a 3-D configuration. Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers. But for years, IBM, Intel and others have been looking at stacking microprocessors, memory and other functions using TSV technology.
Chip makers have experienced stumbling blocks in that arena. According to John Knickerbocker, a distinguished engineer from IBM Corp., here’s five challenges for 3-D devices based on TSVs:
1. Lack of EDA design tools. ”There is room for growth in design tools.”
2. Complexity of designs. The industry is making 3-D devices with relatively few TSVs, but the key is to make parts ”with thousands of TSVs.” Drawing heat out of such a complex 3-D design is also a challenge.
3. Integration of assembly and test. It’s unclear if 3-D chips based on TSVs will be produced by the IDMs, foundries or IC-assemblers, but one thing is clear: ”Test is a challenge for everyone.”
4. Heterogeneous system integration. The challenge is to integrate different chips–such as ”RF, memory and the MPU”–in one part.
5. Standards. SEMI has standards. Sematech has different specs. Others are moving in their own directions.