by Robert J. Safranek and Michelle J. Moravan
In early generation Intel systems traffic was broadcast across the shared, bi-directional “Front Side” Bus. With many sources driving the bus, electrical constraints made improving Intel FSB performance a challenge. Techniques included increasing the bus clock frequency and transferring requests at two and four times the bus clock rate, called double- and quad-pumping respectively. As systems grew to include many sockets, more busses were added, first two per system, called dual independent buses (DIB), and then eventually at a one to one ratio, creating a dedicated high-speed interconnect (DHSI) between each socket and the chipset.
With ever-increasing numbers of cores, the system demand for memory bandwidth exceeded the capabilities of a single memory controller. At this point, additional transistors provided by smaller process technologies made it economical to integrate the memory controller on-die, implying at least one per socket. The Intel FSB changes required to support multiple memory controllers would have relinquished full backwards compatibility. Without the need to maintain full backwards hardware compatibility, the system architects had an opportunity to introduce an entirely new interconnect paradigm: the inception of the Intel QuickPath Interconnect.
