By Timothy Prickett Morgan
IBM likes to go on and on about the transaction processing power and I/O bandwidth of its System z mainframes, but now there is a new and much bigger kid on the block. Its name is the Power Systems IH supercomputing node, based on the company’s forthcoming Power7 processors and a new homegrown switching system that blends optical and copper interconnects.
Each Power7 core has 12 execution units: two fixed point units, two load store units, four double-precision floating point units, one vector unit (for doing matrix maths), and one decimal floating point unit (for doing money maths). Those floating point units, like those in all past generations of 64-bit Power processors that trace their heritage back to IBM’s AS/400 designs from 1995 can do two floating point operations per clock cycle.
The Power7 core has 32KB of L1 instruction cache and 32KB of L1 data cache. Each core sports simultaneous multithreading that delivers four virtual threads per core, and has a 256KB of L2 cache tightly coupled to it. The chip also has 32MB of embedded DRAM that acts as a shared L3 cache, with 4 MB segments affiliated with each of the eight cores. The Power7 chip has two dual-channel DDR3 memory controllers implemented on the chip, which deliver 100 GB/sec of sustained bandwidth per chip.
