by Anand Lal Shimpi, AnandTech
This is the Bulldozer building block, what AMD is calling a Bulldozer Module:
AMD refers to the module as being two tightly coupled cores, which starts the path of confusing terminology. A few of you wondered how AMD was going to be counting cores in the Bulldozer era. There are two independent integer cores on a single Bulldozer module. Each one has its own L1 instruction and data cache (thanks Johan), as well as scheduling/reordering logic. AMD is also careful to mention that the integer throughput of one of these integer cores is greater than that of the Phenom II’s integer units.
Intel’s Core architecture uses a unified scheduler fielding all instructions, whether integer or floating point. AMD’s architecture uses independent integer and floating point schedulers. While Bulldozer doubles up on the integer schedulers, there’s only a single floating point scheduler in the design.
Behind the FP scheduler are two 128-bit wide FMACs. AMD says that each thread dispatched to the core can take one of the 128-bit FMACs or, if one thread is purely integer, the other can use all of the FP execution resources to itself.
