by Michael W. Jones
Giant chip-maker Intel has been buying up specialty software companies in an effort to gain additional expertise in writing software for the multi-core processors that make up most of their lineup of CPUs.
The first of these was actually back in June, making for a total of three, when Intel purchased Wind [...]

[Read more →]

Chip makers will describe plans to deliver server processors with eight CPU cores at the Hot Chips conference at Stanford University next week, though there is some debate about what the products will mean for end-users.
On Tuesday, IBM will give the first detailed look at the Power7, a follow-on to the Power6 introduced two years [...]

[Read more →]

Roman Dementiev explains a simple technique he used for improving the scalability of his workload. His VTune™ analysis of the workload reveals that the top hot functions in the code were mmap, munmap and memset. However, his application does not use memory mapped files. The reason for existence of these functions is that the Linux [...]

[Read more →]

by Paul Clarke
Large investment banks are likely to increasingly look towards hardware acceleration for low latency solutions in a bid to shave milliseconds off trading times. This move is imminent, suggest commentators, but sadly any job creation is still a little way off.
“Software cannot be optimized any more than it has been already, nor can [...]

[Read more →]

by Michael Wolfe, PGI Compiler Engineer
“The first installment of this series introduced the PGI Accelerator Programming Model, showing three simplfiee programs in C and in Fortran, and presenting a few details of building and running a program on the GPU. Here we discuss some issues affecting performance and how to recognize and address them. [...]

[Read more →]

Here is an article written by The Portland Group’s Brent Leback, Steven Nakamoto and Michael Wolfe for introducing their Accelerator programming model for multicore. This was published in June’s (2009) news letter. They list five categories of programming methods for multicore. They are:
* Use a parallel-optimized library: (eg. BLAS)
* Use a parallelizing compiler
* Use [...]

[Read more →]

Grid and cluster computing management software company Platform Computing has inked a distribution agreement with graphics chip maker nVidia. It will see the HPC expert bundle nVidia’s CUDA programming environment with its cluster management tools and integrate it into those tools.
The move will allow Platform Computing’s Load Sharing Facility (LSF), the backbone of its open [...]

[Read more →]

Sony on Tuesday announced that it was upping the ante in the next-generation console war, unleashing the slender PS3 slim. Eschewing the original PS3’s bulbous design, the new console reportedly will drop Linux support and also won’t support PS2 games. The console does bring a greater capacity 120 GB drive onboard, though, a [...]

[Read more →]

Nvidia’s corporate strategy firmly rests on expanding the market for GPUs beyond graphics to include certain types of computation. Specifically, Nvidia’s efforts with CUDA are aimed at moving GPUs into the high performance computing (HPC) market – where the substantial compute capabilities and memory bandwidth directly translate into performance. Nvidia’s Tesla products (GPUs designed for [...]

[Read more →]

by Michael Feldman, HPCwire Editor
As IT budgets have gotten squeezed, more customers are looking at cloud computing as a way to avoid up-front capital costs, while getting access to as many CPU cycles as they need. In response, all the big IT firms are scrambling to develop a cloud computing product and services strategy, [...]

[Read more →]

by Mark Parsons
The transition from serial to parallel programming is difficult, and as a result the number of programmers trained to develop code in this way has remained less than 1% of the overall programmer population.
For most businesses and individuals, the introduction of multicore processors has been positive. However, more technical users have not reaped [...]

[Read more →]

Recently there have been a few articles citing the challenges of multicore (Desktop multiprocessing: Not so fast) and a report (Multicore Is Not the Panacea for Increasing Performance [$3500]) from MarketResearch.com. While we post links to these articles on MulticoreInfo.com because they are multicore related information, it does NOT mean to discourage or to play [...]

[Read more →]

Green Hills Software, has just made available a new firmware release of its Green Hills Probe hardware-assisted microprocessor debugging solution.
Used in combination with its MULTI software development environment, the probe is designed to allow software developers to gain the control and visibility required to perform board bring-up, device driver development, and other system debugging tasks [...]

[Read more →]

Did you know that Intel® Parallel Advisor Lite offers you the ability to prototype (model) parallelism in your serial application? It lets you scope the effort of parallelizing your application while continuing to use your existing test system and debugging tools as you make source modifications to avoid data sharing issues.
To model potential parallelism, you [...]

[Read more →]

Silverlight 3 doesn’t offer native support for loading and rendering 3D models. However, Balder offers a very complete managed 3D engine for Silverlight 3. It achieved the necessary frame rate taking advantage of Silverlight’s threading capabilities.
Balder doesn’t use the GPU (Graphics Processing Unit) to render 3D models. It uses a software rendering process. Silverlight 3 [...]

[Read more →]

The Rapidmind founders, engineering team and marketing team have joined Intel this week. Intel has acquired the Rapidmind products and technology. Rapidmind proved itself to be an innovative company with advanced technology for helping software developers with data parallel programming for multicore processors and accelerators. Their joining Intel will let us do even greater things [...]

[Read more →]

By Chris Lee, Ars Technica
One of the ever-present trends in electronics is that stuff gets smaller. Although it doesn’t get much attention, the fact that electronic features can be scaled continuously in size down to something very close to the single atom level is an important reason why electronic devices are still king. The pretenders [...]

[Read more →]

By Andrey Marochko
Just released TBB 2.2 (feel free to download its open source version from the official TBB site) utilizes the new C++ exception propagation functionality that is part of the upcoming C++0x standard, and thus makes exception handling in TBB based applications even more straightforward. Of course the new mechanism will work only when [...]

[Read more →]

During his two tech sessions at Game Developers Conference (GDC 2009), Intel’s Steve McCalla talked a lot about SIMD programming with Larrabee. Afterwards he answered a few questions which had to do with rasterization, vectorization and more.

Related Articles
Larrabee: A Many-Core x86 Architecture for Visual Computing [Whitepaper]
A First Look at the Intel Larrabee New [...]

[Read more →]

During GDC’09 in Cologne, Edmund Preiss from Intel shows how Intel Parallel Studio works.

[Read more →]