You could say mobile chip makers are trying to kill one bird with two stones. In order to give smartphones enough computing power for the myriad new software applications and features consumers crave, companies making the semiconductors that run cell phones are doubling the number of processors on each chip. The technological leap will offer [...]

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The 2009 Symposium on Application Accelerators in HPC will be held in July (20th to 30th) in Urbana, IL.
“What do GPUs, FPGAs, vector processors and other exotic special-purpose chips have in common? They are advanced processor architectures that the scientific community is using to accelerate computationally demanding applications. While high-performance computing systems that use [...]

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by Greg Pfister
“Accelerators have always been the professional wrestlers of computing. They’re ripped, trash-talking superheroes, whose special signature moves and bodybuilder physiques promise to reduce diamond-hard computing problems to soft blobs quivering in abject surrender. Wham! Nvidia “The Green Giant” CUDA body-slams a Black-Scholes equation financial model! Shreik! Intel “bong-da-Dum-da-Dum” Larrabee cobra clutches a fast [...]

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In late June 2009, at the University of Illinois Urbana-Champaign’s Universal Parallel Computing Research Center Summer School for Multicore Programming team produced a top notch event that immersed all of the participants in the fundamental of parallel programing.
UPCRC Co-Director Marc Snir kicked it off with an Introduction to Parallelism. His broad overview touched on many [...]

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It’s well known that 32nm Intel Nehalem-class mobile CPU+GPU goodness will debut in Q1 2010, but what notebook-oriented processors will the chip giant introduce?
We’re anticipating around send ‘Arrandale’ processors to be launched early next year with both Core i5 and Core i7 branding. Members of both families will target performance laptops in both the low-voltage, [...]

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In a press release, IBM today announced new systems software for managing virtualized servers, designed to help clients plan, build and maintain data centers while reducing costs. IBM is also helping clients protect their long-term investments in Power Systems™ by announcing an upgraded path to its next-generation servers that will include POWER7 microprocessors.
The new systems [...]

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Source: SoftTalk
Many consider that Software Transactional Memory (STM) is a promising technology to help accelerate the creation of parallel applications. STM can benefit from additional real world testing and feedback to assist developers new to parallel programming.
Parallel programming has traditionally been considered using locks to synchronize concurrent access to shared data. Lock-based synchronization, however, has [...]

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Catamount N-Way (CNW) Lightweight Kernel, developed at Sandia National Laboratories wins this year’s R&D 100 awards. This leverages hardware capabilities of multicore processors to deliver significant improvements in data access performance for parallel computing applications. CNW provides enhanced data access capabilities beyond other equivalent operating systems by employing a new technique that targets memory bandwidth, [...]

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Cilk Arts teamed up with MIT’s Professional Development Program on a 2-day workshop focused on multicore programming. Here is the video of second day’s lecture.
The first two lectures can be watched at Lecture 1 and Lecture 2.
The third lecture covered:
* Implementation of Cilk Loops
[...]

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by John West, insideHPC
Release 9.0 of PGI’s compiler gives programmers access to the PGI Accelerator Programming model, an innovation that the company feels does “for GPU programming what OpenMP did for thread programming.” The idea is that programmers need only add directives to C and Fortran codes, and the compiler does the rest. Of course [...]

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The Intel Academic Community announced the launch of its center of excellence for faculty training at M S Ramaiah Institute of Technology (MSRIT), Bangalore, India.
This Center of Excellence at the MSRIT campus which is fully equipped with latest Intel hardware and software aims to train 300 faculties from 155 institutes of Visveswaraiah Technological University (VTU) [...]

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REvolution Computing said it will be giving a workshop titled “Parallel Computing in R,” and demonstrating how to deploy R programming across multiple workstations and clusters to ramp up speed computations at Bioconductor (BioC 2009) July 27 to 28 at the Fred Hutchinson Cancer Research Center in Seattle. It will also demo the use of [...]

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by Stephen Blair-chappell
When changing code from serial to Parallel, it’s easy to introduce new types of errors; data-races and deadlocks. Fortunately there are a number of tools that can be used to detect these. This article explains Static and Dynamic analysis to help spot the problems.
In Static analysis a sort of ‘automatic’ code inspection is [...]

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David E. Ott
In this brief technical paper, the author provides an overview of the NUMA shared memory architecture and describe various techniques for optimizing application memory performance within a NUMA-based system. In particular, he discusses the role of processor affinity, memory allocation using implicit operating system policies, and the use of the system API’s for [...]

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Here is the first part of a series of articles written by Tim Mattson that provide the information you need to correctly use and understand the jargon that has sprung up around parallel computing.
Concurrency: A property of a system in which multiple tasks that comprise the system remain active and make progress at the same [...]

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Originally Posted on June 24th, 2009
We provided many resources of parallel programming tutorials. The following are the ones we have linked so far.
Basic parallel computing tutorial
MapReduce tutorial
Cell processor programming
OpenMP tutorial
PThreads Tutorials
In Part 6, we provide links to Intel Threading Building Blocks (TBB).
TBB offers a rich and complete approach to expressing parallelism in a C++ [...]

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Microsoft Research recently announced the availability, under Academic Licensing, of Dryad, an infrastructure which allows a programmer to use the resources of a computer cluster or a data center for running data-parallel programs. A Dryad programmer can use thousands of machines, each of them with multiple processors or cores, without knowing anything about concurrent programming.
DryadLINQ [...]

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Clay Breshears and Michael Wrinn hosted this parallel programming talk show. The guest was Michael Voss, Ph.D. Mike is an engineer in the Performance, Analysis and Threading Lab at Intel. He is one of the senior developers on the Intel® Threading Building Blocks team. We asked Mike what was going to be new in the [...]

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Intel Corporation on July 17th announced the successful completion of its acquisition of Wind River Systems Inc. Wind River is a leading software vendor in embedded devices, and is part of Intel’s strategy to grow its processor and software presence outside the traditional PC and server market segments into embedded systems and mobile handheld devices. [...]

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Managing application layer shared resources on a multicore chip requires features that include synchronization primitives and memory allocation and management. Most OSs provide rich resource management features, but many multicore programmers must work within systems that use multiple OSs because the cores have different instruction sets, because the memory is not uniformly accessible by all [...]

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