The semiconductor memory industry is about to experience major technological changes as three-dimensional multi-gate structures push transistors and memory architectures forward, according to a one-day memory workshop held last month in Grenoble, France, by leading researchers from around the world.
Traditionally, CMOS downscaling has had the double benefit of increasing device performances and reducing power consumption. This trend has, however, reached its limits. The devices’ copper interconnects are introducing problems of crosstalk, power consumption and resistive-capacitive delay.
Meanwhile, the motivations for going into the third dimension have increased since the technology achieves smaller form factor with increased package densities to meet bandwidth, radiofrequency, power consumption performance improvements while keeping cost reduction targets. Through-Silicon-Via (TSV) wafers have the potential to represent as much as 25 percent of the memory business by 2015.
