By John Blyler and Pallab Chatterjee
Consumers love ever-smaller electronic products that have longer battery life and more features. For the chip developer, these “loves” translate to increased circuit performance and higher transistor density at lower and lower technology nodes, such as 45nm, 28nm and beyond. But these nodes are fraught with design and manufacturing challenges that weren’t really a problem at the relatively spacious geometries of 130nm and above.
As transistors shrink to deep submicron sizes and – more importantly – the interconnects between them become several hundred atoms wide, problems with parasitic effects become paramount. Designs must now gather very accurate models to extract parasitic information about resistance, capacitance and inductance in the nano-size circuit. At smaller geometrics, the effects caused by parasitics become more pronounced which means that the accurate modeling of these effects becomes more important.
