To enable chip scaling, there is always brute-force lithography. During a presentation on Friday (June 26), chip-making consortium Sematech outlined other and futuristic ways to enable Moore’s Law.
Here are some of the proposed options for transistor-level scaling:
1. Zero low-k interface
2. Single metal gate stack
3. Gate stacks on III-V semiconductors
4. Quantum-well MOSFETs
5. 3-D chips using through-silicon-via (TSVs)
