By John Nieto, Inphi Corp for EDN
Applications demanding higher system bandwidth and lower power, such as converged notebooks, desktop PCs, and servers, continue to drive the evolution of industry standards, including DDR3 (double-data-rate 3), as the JEDEC (Joint Electron Device Engineering Council) Solid State Technology Association defines it. The latest DDR3-memory standard, JEDEC JESD79-3A, supports these needs and the requirements of emerging dual-core- and multicore-processor systems. DDR3, the latest DDR-memory-interface technology, differs from the well-established DDR2 standard in several areas, including data rate, operating voltage, and logic
DDR3 uses eight internal banks compared with DDR2’s four to further speed systems by allowing advance prefetch, which reduces access latency. This speed should become more apparent as the size of the DRAM increases in the future. The I/Os for DDR3 use the JEDEC standard SSTL (stub-series-terminated logic) 15, which employs 1.5V logic, whereas DDR2 uses JEDEC standard SSTL18, which uses 1.8V logic. The DDR3 architecture fully uses ODT (on-die termination), ZQ (zero-quotient) calibration, and a fly-by topology for improved signal integrity. With such a high demand for lower-power memory and cost-saving technologies, JEDEC is now defining a DDR3L (DDR3-low-voltage) node.
