Synopsys has increased verification speed and brought digital, analogue and memory simulation under the same roof as it moves its tools to multi-core hosts.
Until now, the simulator used for verification has run on a single processor. “There are activities running in the background that sit and watch, and only in some cases have to make an action - to indicate an error for example,” said Smith. “What we have done with the simulator is to run it in parallel in multiple processor cores.” Monitoring activities now run on cores away from the simulator, sniffing simulated states through shared memory. “So long as the memory is big enough, it runs fast,” said Smith. “We have tested this on up to eight cores - primarily because most computer servers max out at eight.”
