by EDN Executive Editor Ron Wilson
One of the fundamental ideas of multicore architecture is that by switching cores on and off or by throttling them, you can match the performance and power consumption of the chip almost exactly to the real-time needs of the task load, to a degree that is not feasible with huge single-core processors. But that promise implies a lot about the foundation. Such an SoC would be a mosaic of independently-controlled voltage and clock domains, all mortared together with interfaces that handle voltage translation, clock boundary crossings, and intricacies such as data retention and non-disturbance.
All the elements of that foundation are in place. And even, to a great extent, the design tools to lay the foundation are in place. (We will look politely away from the verification question for now.) But what seems to be missing is a unified, standardized way to control all those regions so that the end-user actually gets the lowest heat dissipation, the longest battery life, or whatever. That was the topic a panel took on at the Multicore Expo.
