By Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, and Amal Zerrouki, Actel
In Part 1 of this series, the authors introduced power-aware FPGA design. In Part 2, they discussed fighting dynamic power. In this last installment of this series, they continue discussion of fighting dynamic power and propose power reduction methodology. Here are some excerpts from their article.

Fighting logic and nets’ dynamic power
Several papers have been dedicated to this subject alone [BASZ2000, Belhadj 2002]. Due to lack of space, the focus of the following sections will be dedicated only to a power profiling of some arithmetic DesignWare elements, and a brief discussion of techniques to eliminate or reduce the propagation of unnecessary glitches.

Power-aware synthesis options/constraints setting
Because of the pressure to meet timing requirements, many FPGA designers do give much attention to the synthesis process and use stringent global timing constraints. This usually leads to larger utilization of the FPGA logic elements and the associated routing resources.