By Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, and Amal Zerrouki, Actel
In Part 1 of this series, the authors introduce power-aware FPGA design. In Part 2, they discuss fighting dynamic power.
Other techniques to reduce RAM power
There are more opportunities to reduce wasted power; in particular, when cascading multiple blocks to build a large RAM, or when the data and/or the address bits are not changing systematically every clock cycle. The following sections address these…

RAM Cascading
FPGAs offer several embedded RAM blocks with unique sizes but variable aspect ratios. This feature opens the door for different cascading schemes. Fig 9 is an illustration of two alternatives that have different timing and power attributes.