by Ioan Raicu, Ian Foster and Yong Zhao, published at International Science Grid This Week
“Tightly-coupled applications for which jobs must communicate between each other during execution are typically best served by clustered High Performance Computing (HPC). Applications with many independent job streams, on the other hand, are better suited to distributed High Throughput Computing (HTC). [...]

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by Bill Schweber for EETimes
Since its pronouncement in 1965, Moore’s Law has been the defining paradigm of the electronics industry. (”Law” is a misnomer, it’s a “conjecture”; F=ma is true law). Under its guidance, we relentlessly drive towards ever smaller features, higher densities, larger wafers and more chips per wafer. Yet there’s a problem with [...]

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Here is a white paper from TotalView Technologies that describes the challenges of race conditions and other difficult bugs in parallel programming. It introduces a product called ReplayEngine.
Abstract
The hardest step in solving software bugs in a parallel programming environment centers on working backward from a software failure to the original program error. Conventional debugging techniques [...]

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What: Tensilica, Inc. will present a live webcast, “Everything You Wanted to Know About SOC Memory - But Forgot to Ask.” The webinar discusses the many alternatives for on-chip and off-chip memory usage that SOC designers must understand to develop successful multicore SOCs. The webinar will also highlight the essentials of SOC memory organizations [...]

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The Centre for Development of Advanced Computing (C-DAC) of India started out with the specific mandate of developing a High Performance Computing (HPC) system and providing HPC solutions for various applications. Today C-DAC has diversified into many other information technology-related activities and has also expanded its portfolio of institutions. C-DAC’s Director General S. Ramakrishnan spoke [...]

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by Michael Feldman, HPCwire Editor
The nascent GPGPU computing world received another boost today with the commercial release of Jacket 1.0, a GPU engine for MATLAB. Jacket was developed by AccelerEyes, a two-year-old Atlanta-based startup that was founded by Georgia Tech grad John Melonakos, who also runs the company. AccelerEyes aims to tap into the [...]

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by Mark Hermeling, Wind River
“This is an argument that will never end, much like C vs C++, VI vs Emacs and Windows vs Mac OS vs Linux. There is no right answer to any of these questions, well, nothing better than ‘it depends’. (though for me the OS war has been won by Apple hands [...]

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During CES a group of overclockers with access to liquid nitrogen and liquid helium for the extra boost of coldness cools an AMD Phenom II X4 chip to -232 degrees Celsius. Once they got the chip cooled to this frigid temperature, they pushed the clock speed all the way up to 6.5GHz, which is a [...]

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ROBOBAK(TM), the leader in agentless data protection software designed for remote and branch offices, today announced that the ROBOBAK Testing Laboratories have validated Intel(R) Corporation’s newly-announced, third-generation Intel(R) vPro(TM) suite of business desktop PC technologies to seamlessly work with ROBOBAK’s v9 Data Protection Suite software.
The verification from the ROBOBAK Testing Laboratories means small- and mid-sized [...]

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AMD is launching new energy-efficient quad-core server processors. The 45nm Quad-Core AMD Opteron HE processors, rated at 55-watt ACP, are designed to help meet the industry’s rising demand for low power, cost-saving data center technology and increased virtualization performance. The new processors are now available in eight server systems from HP and additional systems [...]

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By Gernot Heiser, OK Labs
Virtualization has been a major factor in the enterprise space for years; several virtualization providers have become billion-dollar companies. More recently, virtualization has started to become a hot topic in the embedded systems areas. This is demonstrated by recent moves of the dominant providers of virtualization for the enterprise, VMware and [...]

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The semiconductor memory IP expert Rambus has pioneered a new memory signaling technologies useful for the development of a future memory architecture capable of delivering a terabyte per second of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC).
To achieve 1 TByte/s memory bandwidth, Rambus has developed fundamental innovations that include,
1. [...]

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The task of familiarizing programmers with the sphere of developing parallel applications is getting more and more urgent. This article is a brief introduction into creation of multi-thread applications based on OpenMP technology. The approaches to debugging and optimization of parallel applications are described.
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As developing parallel software is rather a difficult task at present, the questions of theoretical training of specialists and investigation of methodology of projecting such systems become very urgent. Within the framework of this article we provide historical and technical information preparing a programmer for gaining knowledge in the sphere of developing parallel computer systems.
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The tool for programmers VivaMP is intended for helping OpenMP-based parallel software developers. The article gives a brief description of the program product.
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Testing parallel software is a more complicated task in comparison to testing a standard program. The programmer should be aware both of the traps he can face while testing parallel code and existing methodologies and toolkit.
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Since multi-core systems are spreading fast, the problem of parallel programming becomes more and more urgent. However, even the majority of experienced developers are new to this sphere. The existing compilers and code analyzers allow finding some bugs, which appear during parallel code development. However, many errors are not diagnosed. The article contains description of [...]

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Shameem Akhter, a platform architect at Intel, and Jason Roberts, a senior software engineer at Intel, are the authors of Multi-Core Programming: Increasing Performance through Software Multithreading. They write an article, which describes the theory and practice of the principal parallel programming constructs that focus on threading and begins with the fundamental concepts of synchronization, [...]

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I have been looking for programming models that would efficiently work for multicore processors. In the last few years many models have been introduced. Among those, which would be general enough to have an impact on multicore programming? In search of an answer, I have found a few articles and research papers. I will go [...]

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In a recent paper, Professor Xian-He Sun reevaluates Amdahl’s law for multicore processors. This paper introduces fixed-time speedup and memory-bounded speedup models to evaluate scalable computing for multicore architectures.
Abstract:
Microprocessor architecture has entered the multicore era. Recently, Hill and Marty presented a pessimistic view of multicore scalability. Their analysis was based on Amdahl’s law (i.e. [...]

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