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Cadence rolls multi-core design solution

December 3rd, 2008 · No Comments




Promising scalability and support for parallel processing across the design flow, Cadence Design Systems Inc. Wednesday (Dec. 3) rolled out a RTL-to-GDSII configurable digital implementation platform geared toward the 45- and 32-nm nodes.

According to Cadence (San Jose, Calif.), the Encounter Digital Implementation System introduces several new and enhanced implementation and design closure technologies. The product also offers automated floorplan synthesis, design exploration and a robust ranking solution to help designers evaluate and choose between floorplan and design options, according to the company.

The Encounter Digital Implementation System incorporates “signoff-quality” variation analysis and optimization across the entire design flow and integrated global diagnostic tools for timing, clock and power consumption analysis and debug, Cadence said.

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Tags: Industry News · MulticoreInfo · Processors

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