Cadence Design Systems, Inc. has launched the Cadence® Encounter® Digital Implementation System, a configurable digital implementation platform delivering incredible scalability with complete support for parallel processing across the design flow. The system also brings an ultra-efficient new core memory architecture delivering higher-performance, higher-capacity design closure for single CPU operations. With this new system, designers are reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices.
Along with enhanced performance and capacity, Encounter Digital Implementation System offers new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow. In addition, multiple new and enhanced implementation and design closure technologies are being introduced, including automated floorplan synthesis, end-to-end multi-mode multi-corner optimization, variation-tolerant and low power clock tree and clock mesh synthesis, high-capacity placement and optimization, 32-nanometer routing and manufacturing-aware optimization, signoff-driven implementation, and flip chip design features.
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Digital implementation platform promises scalabilities
