Modern microprocessors split up and access memory (RAM) in a somewhat complicated, multi-tiered manner. Most microprocessors include one, two, or even three levels of cache, which are used to temporarily hold recently or often accessed areas of main RAM. These different levels of cache run at different speeds and are configured in different sizes depending on the make and model of the microprocessor. All ordinary microprocessor memory access goes through these caches. Although in most cases the cache architecture makes itself transparent and allows software to run optimally without any special care from the software designer, there are cases where taking the cache architecture into consideration can result in significant software performance improvement. Here is an article by Greg Fry, which first explores the AMD microprocessor cache architecture and then covers code construction techniques that are designed to be cache-friendly, thus producing optimal code execution speed.

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(Published on AMD Dev Central on 09/04/2008)