Tom Halfhill, Senior Editor of Microprocessor Report writes that We keep hearing more complaints that it’s hard to write software for multicore processors because there aren’t enough development tools. Not enough tools? That’s like complaining it’s hard to buy Chinese products because there aren’t enough Wal-Marts. The real problem with multicore processors is too many [...]

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This morning a new Parallel Programming talk radio show on the Intel Software Network. Aaron Tersteeg of Intel says that the idea is kind of a cross between Car Talk and Love Lines. The goal of this show is to provide some getting started information, share new innovations in parallel programing and talk with people [...]

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Mindspeed Technologies, Inc. today announced that it has achieved industry-leading performance for power-sensitive applications through an ongoing collaboration with ARM in designing Comcerto 100 broadband gateway processors. The Comcerto 100 provides the leading performance-power-cost profile in its class, delivering 2 Gbps at 1.7W power with two channels of voice-over-IP (VoIP).
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Data-processing operations are at the heart of any multimedia application. So expanding on the discussion in Part 1, this part discusses the impact of the pipeline delay characteristics on the coding style in a variety of operations such as Fast Multiply Operations, Fast Multiply and Accumulation, Double-Word Loading and Storing, Scheduling Load and Store Multiple, [...]

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Questions regarding AMD’s “asset-smart” strategy are once again being asked, as rumors concerning the possible spin off of AMD’s manufacturing entities into a separate company reemerged after an Austin, Texas-based newspaper in mid-July wrongly reported that the company’s newly appointed CEO Dirk Meyer had confirmed fabless plans.
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The Weather Research & Forecasting Model (WRF) is the most widely used model in the world. NCAR’s climate and weather models are moving from Terascale (1 trillion FLOPS) to Petascale class applications. The problem has been particularly acute with applications that involve a real-time component or other time-to-solution constraints. In examining ways to improve overall [...]

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The University of Illinois at Chicago is hosting a live high-definition (HD) feed of a summer school on petascale computing being taught from the National Center for Supercomputing Applications (NCSA) at the University of Illinois at Urbana-Champaign, August 18-22. Organizers of the weeklong intensive summer school, titled “Accelerators for Science and Engineering Applications: GPUs and [...]

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In March, Microsoft’s External Research Team put out a request for proposal (RFP) for three-year research projects in multicore computing. The award winners were announced in June. On July 28, the opening day of its annual Research Faculty Summit, Microsoft mentioned more on how and where it will be spending its grant money.
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Here is an interview with Garth Gibson on faster storage systems. Garth Gibson has devoted a career to looking at ways to use parallelism for faster and more reliable storage. Gibson is on the faculty of Carnegie Mellon University’s computer science department, and is cofounder and chief technical officer of Panasas.
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At the ninth annual Microsoft Research Faculty Summit today, Tony Hey, corporate vice president of Microsoft’s External Research Division, emphasized the role his group plays not only in supporting specific collaborative research projects, but also in improving the process of research and its role in the innovation ecosystem. He also discussed collaborative initiatives intended to [...]

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VMWare today announced its stand-alone ESXi hypervisor will be available at no cost to help companies of all sizes experience the benefits of virtualization. Raghu Raghuram, vice president of products and solutions, VMware said, “With the explosive growth of multi-core capacity, improvements in virtualization-aware hardware, and performance improvements in our virtualization software, we believe that [...]

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Rob Farber writes about CUDA programming for Dr. Dobb’s. In Part 5 of this article series on CUDA (short for “Compute Unified Device Architecture”), he discussed memory performance and the use of shared memory in reverseArray_multiblock_fast.cu. In this installment, he examines global memory using the CUDA profiler.
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The Internet doesn’t play favorites. In principle, consumer computing devices can use any processor powerful enough to run a full-featured browser. In practice, however, two contenders stand head and shoulders above the rest: ARM, the champion of handsets, and Intel, king of the PC. The clash between these titans will be a battle of epic [...]

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The Berlin-based Ferdinand Braun Institute for Ultra-High Frequencies (FBH) has developed a semiconductor process that enables transistors switching at frequencies of well beyond 200 GHz. The process has another capability which could be of interest to the semiconductor industry: It enables chip designers to create three-dimensional integrated circuits.
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To get around the inter-chip networking bottlenecks, companies like Intel and Rambus have been working on prototypes of newer architectural models of chip design. Rambus has a model called Terabyte Bandwidth Initiative (TBI) and Intel’s programme is called Terascale Computing Research Program.
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Perl creator Larry Wall promised version 6 of Perl will be the first truly extensible programming language during his annual “State of the Onion” speech at the O’Reilly Open Source Conference (OSCON). One of the new features touted included a much more friendly set of error messages, as well a way [...]

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Intel is ready to charge once more unto the breach of system-on-a-chip (SoC) devices, this time with a new line of embedded processors based on the same instruction set used in all its desktop and mobile products. The chipmaker will release eight new x86-based SoC processors targeted at security, storage, and communication gear, as well [...]

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NVIDIA is continuing to push hard on CUDA, the company’s C-based software environment for GPU computing. Michael Feldman, the editor of HPCwire, writes in his blog about NVIDIA’s research initiatives at UIUC, Visual Buddy at Argonne, and their manycore war of words.
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The IBM Blue Gene/P Intrepid — the fastest computer in the world for open science and the third fastest overall computer in the world — at the Argonne National Lab will soon have advanced data analytics and visualization capabilities, thanks to a recent contract awarded to GraphStream and the world’s largest installation of NVIDIA Quadro [...]

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The PowerPC 460S allows the system-on-chip (SoC) designer to select the L2 cache size, L1 cache size and multicore processor local bus necessary to optimize their design. The IBM PowerPC 460 and cache-configurable PowerPC 405 embedded microprocessor cores will be components of the Synopsys DesignWare Star IP programme.
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