NEC Corporation today announced the development of an important new technology that is able to “visualize” the thermal distribution and reduce the power consumption of LSI, which has become an increasingly serious challenge as the miniaturization of LSI continues to advance. These latest developments have been demonstrated through NEC’s SX-9 supercomputer.
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AMD has got over its quad-core delivery problems and is now shipping that device in volume. Mario Rodrigues writes to ITExaminer.com about what AMD might have done differently.
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The AMD64 direct connect architecture was designed to support up to eight sockets without any intervening core logic. Mario Rodrigues here writes about if only one Opteron chip was going to be used it had to be installed in the primary socket.
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Here is a two part article by Michael Wall, Principal Member of Technical Staff of AMD. In Part I he discusses 64-bit optimization, multi-core, threading 101, vectorization, software profiling using AMD CodeAnalyst™ and assembly code. In Part II, he discusses Memory Optimization.
Part 1 link
Part II link
Software Guide for AMD Family 10h Processors

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As multicore computers become more commonplace, running an application that has only one path of execution for code to follow quickly becomes a barrier to performance. In order to take advantage of a computer’s extra cores, an application must break its overall work down into smaller chunks and run those chunks concurrently on separate cores. [...]

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Recent years have seen an end to the continual rise of processor clock speeds, and a move toward multi-core as the way forward. This trend has implications for software developers, because in order to make use of the extra processing power available in multi-core systems, you have to rewrite parts of your application to work [...]

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MIPS Technologies, Inc. announced that a MIPS(R)-optimized release of Sourcery G++, a complete C/C++ development environment based on the GNU Toolchain and the Eclipse(TM) IDE, is available now from CodeSourcery, Inc.The release supports all MIPS cores, including performance enhancements in the MIPS32(R) 24K(R) core and the superscalar MIPS32(R) 74K(TM) core, as well as other optimizations. [...]

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Michael Feldman of HPCWire writes about one of the final panel sessions at the International Supercomputing Conference (ISC) last week, which was focused on “green” supercomputing, a term used to encompass both power efficiency and environmental responsibility.
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Software systems seem to be ruled by a fundamental law: As they get larger, their complexity increases exponentially. The reason for this is actually simple: Complexity is due not just to the number of parts in the system, but also to the relationship between the parts. Event-Based Architectures (EBAs) simplify system design, development, and testing [...]

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A Taiwanese publication is reporting that Intel (NASDAQ: INTC) plans to release three Nehalem quad-core processors at the end of the fourth quarter, complete with specs on the new chips. DigiTimes, based in Taipei, cited motherboard vendors as its sources, many of which are also based in Taipei.
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Its possible to take advantage of multi-core CPUs by programmatically setting their affinity inside your applications. Here is a blog discussing on how to do it.
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As discussed in The multicore crises: Scala vs. Erlang, massage passing and the actor model of concurrency is one promising way for the massive parallelization needed to utilize current and especially future CPUs. Erlang has it built in from the start and Scala incorporated the Scala Actor library into it’s framework. But there is also [...]

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Earlier in Part 1, Andy described in an article written for Embedded.com the benefits of leveraging virtual platforms to validate architecture, performance and embedded software. In this second part, a case study is provided as a means to illustrate the concepts and benefits of using a well-modeled virtual platform of a simple system-on-chip (SoC) design.
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The road to a faster Internet, data center, and personal computer is paved with silicon. Or so believe researchers at Intel who have unveiled a test chip–made entirely from silicon–that can encode 200 gigabits of data per second on a beam of light.
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Doug Eadline writes an introductory article about Erlang Programming language for Linux Magazine. He says “When one writes an procedural program (C, Fortran, Perl, etc.) you are “closer to the hardware” and farther away from your problem. When you add MPI, OpenMPI, or Pthreads you have moved closer to the hardware and further away from [...]

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Rogue Wave Software, Inc. today announced a solution that will address the need to move millions of existing C++ installations to multi-core hardware and to benefit from significant performance enhancements. Rogue Wave has ported and certified its Hydra Product Suite to the Solaris ™ Operating System (OS) on x86.
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Microsoft Research last month announced the recipients of the Safe and Scalable Multicore Computing RFP awards, totaling $1,500,000 in funding over three years. Here are the award winners.

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Microsoft has a multi-pronged campaign to get in front of multicore. They’re hiring smart people and spending real money. Here is an article talking about their research investment and their own efforts.
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Mentor Graphics Corporation today announced immediate availability of the Questa® Codelink(TM) product, an addition to the Questa Functional Verification Platform designed to speed the validation of ASICs containing one or more embedded processors. The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests.
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EnvironmentTilera Corporation, developer of the breakthrough TILE™ family of high-performance processors for the embedded market, today announced its release of the Multicore Development Environment™ (MDE) 1.3. The new MDE release includes multiple enhancements to the run-time software and a new Ingress Packet Processor (IPP) library.
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