Here is a cache of how-to and technical articles from Embedded.com on multithreading, multicores, multiprocessor-on-chip (MPoc), and multiprocessor system designs. We’re constantly updating our lists of articles and industry links. Links to many articles were posted on www.multicoreinfo.com in the last few months, but Embedded.com has links prior to 2007 that are useful.
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The traditional approach to application performance was to simply wait for the next generation of processor. Most software developers did not need to invest in performance tuning, and enjoyed a “free lunch” from hardware improvements. With the industry shift to multiple core systems, the situation has changed: performance has to be realized through concurrency, with [...]

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Here are slide of a presentation done by David Dagastine and Paul Hohensee at 2007 JavaOne Conference. The presentation discusses multicore architectures, the Java Virtual Machine technologies, and software optimization techniques to make applications run their fastest on multicore platforms.
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The Threading Methodology used at Intel has four major steps: Analysis, Design & Implementation, Debugging, and Performance Tuning. These steps are used to create a multithreaded application from a serial base code. There hasn’t been much written about how to do the Design & Implementation part of the process. Clay Breshears writes for Intel [...]

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Shahzad Bhatti lists a few features that are being postulated as the panacea of multicores. The list includes Multi-threading, Software Transactional Memory, Actor Based Model with Message Passing, TupleSpace based model, Fork/Join, Messaging Middleware (ESB), and Compiler based parallelism.
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Intel’s figures show that increasing a processor’s clock speed by 20 percent provides a 13 percent performance boost but a 73 percent jump in power consumption. If clock speed is dropped by 20 percent, there will be a 49 percent reduction in power consumption but only a 15 percent drop in performance. However, although the [...]

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As most high performance computing users are aware, the rise of multicore-based systems has spawned a number of problems. One of the most fundamental of them is the memory bandwidth bottleneck. Acumem, a two-year-old Swedish company that operated in semi-stealth mode until recently, has released a new performance analyzer specifically developed to help programmers achieve [...]

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Intel on said it would release eight technical papers describing key findings from the company’s work on future programmable multicore architectures.
The papers will be published in the Intel Technical Journal and will provide details on how the company expects future microprocessors with simplified parallel programming models to evolve. With the commodity server market moving quickly [...]

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As Wall Street turns to multicore processors to handle growing data volumes and reduce latency, firms are having a hard time finding programmers with expertise in writing code for parallel processing applications.
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Intel has delayed the first customer shipments (FCS) of its “Montevina” chipsets, part of the new Centrino 2 platform. Peter Glaskowsky writes on CNet that Intel could have discovered a design flaw in the first production units severe enough to prevent them from being shipped.
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x86 microprocessors may not have the absolute lowest power per megahertz, absolute highest performance per clock tick, or optimum code efficiency when you evaluate them against all possible alternatives. Bundle up the features, though, and the total “kit” often stacks up favorably versus the competition. Brian Dipert writes for EDN about the historical trends, current [...]

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Although multicore embedded architectures have emerged as a promising solution to this problem, they bring with them the challenge of developing software that efficiently uses them. Kaushal Sanghai et al. write for EDN that understanding the data-access pattern of an application can help you effectively use the memory and system resources of the underlying architecture [...]

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Social networking technologies, web mashups, multicore and hybrid processors and cloud computing are amongst the ten most disruptive technologies that will shape the information technology (IT) landscape over the next five years, according to research and advisory firm Gartner, Inc.
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Two key server deals and some impressive new benchmark data for the quad-core Opterons provide AMD with a much-needed boost as it looks to regain some of the steam lost to last year’s production delays.
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A consortium of 9 industrial partners and research institutions has received a 4 million euro subsidy to conduct a three-year research project aiming to simplify parallel programming by developing integrated Transactional Memory (TM) systems for multicore computers.
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Cloud computing, the buzz phrase for the burgeoning trend of supplying computing software and services over the Internet – depicted as a “cloud” in many charts – rather than on your own computer. Here is an article that talks about its impact on environment due to huge data centers.
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Multicore devices are driving into embedded applications with new quad core chips from Intel and Renesas and the coming launch of benchmarking for multicore systems. Nick Flaherty reports.
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The Multicore Association is kicking off an effort to define best programming practices for embedded multicore processors. The group hopes within a year to define and create a guide to handling the thorniest problems in the growing arena of parallel software. Here is a news article on EETimes.
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While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM’s Systems and Technology Group, explained the economic considerations behind 3D microprocessors at the ConFab 2008 in Las [...]

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ARM today announced a major technology licensing agreement with Toshiba Corporation encompassing the ARM(R) Cortex(TM) -A9 processor, the Cortex-R4F processor, NEON(TM) SIMD technology, PrimeCell(R) peripherals and CoreSight(TM) on-chip trace and debugging technology.
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